| Message ID | 63d85cc76d4cdc51e6c732478b81d8f13be11e5a.1687551881.git.pawan.kumar.gupta@linux.intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/i386: Export MSR_ARCH_CAPABILITIES bits to guests | expand |
Queued, thanks. Paolo
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1242bd541a53..66d6062aea7c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1049,10 +1049,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", "taa-no", NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", NULL, "fb-clear", NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + "pbrsb-no", NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, .msr = {
On Intel CPUs there are certain bits in MSR_ARCH_CAPABILITIES that indicates if the CPU is not affected by a vulnerability. Without these bits guests may try to deploy the mitigation even if the CPU is not affected. Export the bits to guests that indicate immunity to hardware vulnerabilities. Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> --- target/i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)