From patchwork Wed Oct 21 10:17:55 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Juha.Riihimaki@nokia.com X-Patchwork-Id: 36520 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A37C1B7B78 for ; Wed, 21 Oct 2009 21:29:41 +1100 (EST) Received: from localhost ([127.0.0.1]:45180 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N0YRl-0001se-DU for incoming@patchwork.ozlabs.org; Wed, 21 Oct 2009 06:29:37 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N0YGb-0006Lx-BR for qemu-devel@nongnu.org; Wed, 21 Oct 2009 06:18:05 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N0YGW-0006Ic-8i for qemu-devel@nongnu.org; Wed, 21 Oct 2009 06:18:04 -0400 Received: from [199.232.76.173] (port=43277 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N0YGV-0006II-RP for qemu-devel@nongnu.org; Wed, 21 Oct 2009 06:17:59 -0400 Received: from smtp.nokia.com ([192.100.122.233]:27351 helo=mgw-mx06.nokia.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1N0YGV-0000WN-0W for qemu-devel@nongnu.org; Wed, 21 Oct 2009 06:17:59 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9LAHpfY013327 for ; Wed, 21 Oct 2009 13:17:56 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 21 Oct 2009 13:17:51 +0300 Received: from smtp.mgd.nokia.com ([65.54.30.8]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 21 Oct 2009 13:17:46 +0300 Received: from NOK-EUMSG-05.mgdnok.nokia.com ([65.54.30.90]) by nok-am1mhub-04.mgdnok.nokia.com ([65.54.30.8]) with mapi; Wed, 21 Oct 2009 12:17:40 +0200 From: To: Date: Wed, 21 Oct 2009 12:17:55 +0200 Thread-Topic: [PATCH 06/12] target-arm: optimize arm load/store multiple ops Thread-Index: AcpSN7ifVXPfHkGdT8SUeCioLDrglg== Message-ID: <54D1051E-4C0D-4EB5-9396-4B094F08626F@nokia.com> Accept-Language: en, en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en, en-US MIME-Version: 1.0 X-OriginalArrivalTime: 21 Oct 2009 10:17:46.0484 (UTC) FILETIME=[BC089B40:01CA5237] X-Nokia-AV: Clean X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 1) Subject: [Qemu-devel] [PATCH 06/12] target-arm: optimize arm load/store multiple ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org ARM load/store multiple instructions can be slightly optimized by loading the register offset constant into a variable outside the register loop and using the preloaded variable inside the loop instead of reloading the offset value to a temporary variable on each loop iteration. This causes less TCG ops to be generated for a ARM load/ store multiple instruction. Signed-off-by: Juha Riihimäki Acked-by: Laurent Desnogues --- loaded_base = 0; @@ -6865,7 +6866,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) if (insn & (1 << 23)) { if (insn & (1 << 24)) { /* pre increment */ - tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_add_i32(addr, addr, tmp2); } else { /* post increment */ } @@ -6918,7 +6919,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) j++; /* no need to add after the last transfer */ if (j != n) - tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_add_i32(addr, addr, tmp2); } } if (insn & (1 << 21)) { @@ -6928,7 +6929,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) /* pre increment */ } else { /* post increment */ - tcg_gen_addi_i32(addr, addr, 4); + tcg_gen_add_i32(addr, addr, tmp2); } } else { if (insn & (1 << 24)) { @@ -6944,6 +6945,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } else { dead_tmp(addr); } + tcg_temp_free_i32(tmp2); if (loaded_base) { store_reg(s, rn, loaded_var); } diff --git a/target-arm/translate.c b/target-arm/translate.c index e5a2881..bae1122 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6852,6 +6852,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } rn = (insn >> 16) & 0xf; addr = load_reg(s, rn); + tmp2 = tcg_const_i32(4); /* compute total size */