From patchwork Wed Jun 17 00:36:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 485237 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2910A1401B5 for ; Wed, 17 Jun 2015 10:41:18 +1000 (AEST) Received: from localhost ([::1]:43474 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z51Po-00024s-DF for incoming@patchwork.ozlabs.org; Tue, 16 Jun 2015 20:41:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z51L4-0003BQ-Je for qemu-devel@nongnu.org; Tue, 16 Jun 2015 20:36:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z51L0-000338-Jb for qemu-devel@nongnu.org; Tue, 16 Jun 2015 20:36:22 -0400 Received: from mail-oi0-f46.google.com ([209.85.218.46]:34888) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z51L0-00032y-DY for qemu-devel@nongnu.org; Tue, 16 Jun 2015 20:36:18 -0400 Received: by oiax193 with SMTP id x193so23614256oia.2 for ; Tue, 16 Jun 2015 17:36:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=6KxmMQg9qxmIes2f+DfveAZb3nRROE6ScVcQ8vb0E14=; b=fuXU3mHtF374toWZaaHT6A5FsO626kc6dqn+PnqCsj6KeN11fdJGFavezuBn6+uz10 0eLbBvTcTI9tMqbdO0v982UStZ70fy50t71V6SazZJ44yu1HmPwCbXwyV+AmQPadQLjK jRdijXIC0KtrzJL27injduGJ5Pbtk9H0WhRG8uNeK9Qc2soeiqWJKjwbTV0jfNYH0mh0 Besc4wiGl6dIK4PkFV9IyAUU3xBumZVo+uSdSMbZ3GQ23tY5BiMWe5Pl0xAvbOZNdhqk k2U2lhFxSXJ4hiFzJgEGFOC2hZ/bWyValwz+X6v+w+B8ZeFdXW9osnx97ux8vGAir+2G uzdg== X-Gm-Message-State: ALoCoQmdhV9EdQZVvPF5NPKIEvMRXs5i1kFx5rmbOx0rU+sy9m7MuNRtzulSzE7kA+gk0ulHJqgY X-Received: by 10.182.143.5 with SMTP id sa5mr2417849obb.62.1434501378029; Tue, 16 Jun 2015 17:36:18 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id jp3sm1383937obb.2.2015.06.16.17.36.17 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jun 2015 17:36:17 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Tue, 16 Jun 2015 17:36:16 -0700 Message-Id: <53331c00d80c7ce9c6a83712348773f1b38fae2b.1434501320.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 2.4.3.3.g905f831 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.218.46 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, zach.pfeffer@xilinx.com, jues@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v3 6/7] arm: xlnx-zynqmp: Add boot-cpu property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a string property that specifies the primary boot cpu. All CPUs except the one selected will start-powered-off. This allows for elf boots on any CPU, which prepares support for booting R5 elfs directly on the R5 processors. Signed-off-by: Peter Crosthwaite --- hw/arm/xlnx-ep108.c | 2 +- hw/arm/xlnx-zynqmp.c | 19 ++++++++++++++++++- include/hw/arm/xlnx-zynqmp.h | 3 +++ 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c index 7a98dd6..f94da86 100644 --- a/hw/arm/xlnx-ep108.c +++ b/hw/arm/xlnx-ep108.c @@ -65,7 +65,7 @@ static void xlnx_ep108_init(MachineState *machine) xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline; xlnx_ep108_binfo.initrd_filename = machine->initrd_filename; xlnx_ep108_binfo.loader_start = 0; - arm_load_kernel(&s->soc.apu_cpu[0], &xlnx_ep108_binfo); + arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_ep108_binfo); } static QEMUMachine xlnx_ep108_machine = { diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 353ecad..0c966da 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -90,6 +90,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) XlnxZynqMPState *s = XLNX_ZYNQMP(dev); MemoryRegion *system_memory = get_system_memory(); uint8_t i; + const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; qemu_irq gic_spi[GIC_NUM_SPI_INTR]; Error *err = NULL; @@ -123,13 +124,18 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { qemu_irq irq; + char *name; object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, "psci-conduit", &error_abort); - if (i > 0) { + + name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i])); + if (strcmp(name, boot_cpu)) { /* Secondary CPUs start in PSCI powered-down state */ object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "start-powered-off", &error_abort); + } else { + s->boot_cpu_ptr = &s->apu_cpu[i]; } object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, @@ -157,6 +163,11 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); } + if (!s->boot_cpu_ptr) { + error_setg(errp, "ZynqMP Boot cpu %s not found\n", boot_cpu); + return; + } + for (i = 0; i < GIC_NUM_SPI_INTR; i++) { gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); } @@ -190,10 +201,16 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } } +static Property xlnx_zynqmp_props[] = { + DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), + DEFINE_PROP_END_OF_LIST() +}; + static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + dc->props = xlnx_zynqmp_props; dc->realize = xlnx_zynqmp_realize; } diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index d042df1..4f14a22 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -52,6 +52,9 @@ typedef struct XlnxZynqMPState { MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; + + char *boot_cpu; + ARMCPU *boot_cpu_ptr; } XlnxZynqMPState; #define XLNX_ZYNQMP_H