From patchwork Thu Oct 24 16:21:12 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Musta X-Patchwork-Id: 285970 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A6D762C00AC for ; Fri, 25 Oct 2013 03:23:37 +1100 (EST) Received: from localhost ([::1]:55253 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZNh9-000742-Ed for incoming@patchwork.ozlabs.org; Thu, 24 Oct 2013 12:23:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZNfJ-0004tf-Lf for qemu-devel@nongnu.org; Thu, 24 Oct 2013 12:21:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VZNfC-00029n-64 for qemu-devel@nongnu.org; Thu, 24 Oct 2013 12:21:41 -0400 Received: from mail-gg0-f179.google.com ([209.85.161.179]:57453) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZNfB-00029c-VH; Thu, 24 Oct 2013 12:21:34 -0400 Received: by mail-gg0-f179.google.com with SMTP id g10so957034gga.38 for ; Thu, 24 Oct 2013 09:21:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=L9jIVtmbZZmEkEG7Zm92L85JcSa4anzBmG0RsHwLnKI=; b=uVO3YUN84sxKuvC/6Rx70Fk6VdxIOyw/h0M9W3xVtsCNI0wgblivJSHNvV2Bnb6LAA k4+JldAkUFuAnLQvWeCO2i42Bt1wTveMbj719nVIrvKt93CvGJ2q2FG1Q8ooQOIoBO/i gu24X9TficMrNclE3Qby2LVqKt6pjCqFVqGcCNDc3MpaCUeciyeftFEBmFfB8WxBW417 g+ndny3FT38SAvQVHei7vfxDaPTNE3QPct6lVqS2wrTVttokhUjEj7H1VWUYNVohloqL ndtR09fDo2d1fCRtvW0yOTrVmFIUOlc3uqLfx00YfUiBDJNH57XFFm3BDxkERKX9eCUF rbmw== X-Received: by 10.236.198.141 with SMTP id v13mr172305yhn.162.1382631678461; Thu, 24 Oct 2013 09:21:18 -0700 (PDT) Received: from [9.10.80.59] (rchp4.rochester.ibm.com. [129.42.161.36]) by mx.google.com with ESMTPSA id e39sm3618273yhq.15.2013.10.24.09.21.17 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 24 Oct 2013 09:21:17 -0700 (PDT) Message-ID: <526948F8.2020609@gmail.com> Date: Thu, 24 Oct 2013 11:21:12 -0500 From: Tom Musta User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 To: QEMU Developers References: <526947CA.4020504@gmail.com> In-Reply-To: <526947CA.4020504@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.161.179 Cc: Tom Musta , "qemu-ppc@nongnu.org" Subject: [Qemu-devel] [PATCH 06/19] Add VSX ISA2.06 xmul Instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the VSX floating point multiply instructions defined by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp. Signed-off-by: Tom Musta Reviewed-by: Richard Henderson --- target-ppc/fpu_helper.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ target-ppc/helper.h | 3 +++ target-ppc/translate.c | 6 ++++++ 3 files changed, 56 insertions(+), 0 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index c9997a3..8135325 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1850,3 +1850,50 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ VSX_SUB(xssubdp, 1, float64, f64, 1) VSX_SUB(xvsubdp, 2, float64, f64, 0) VSX_SUB(xvsubsp, 4, float32, f32, 0) + +/* VSX_MUL - VSX floating point multiply + * op - instruction mnemonic + * nels - number of elements (1, 2 or 4) + * tp - type (float32 or float64) + * fld - vsr_t field (f32 or f64) + * sfprf - set FPRF + */ +#define VSX_MUL(op, nels, tp, fld, sfprf) \ +void helper_##op(CPUPPCState *env, uint32_t opcode) \ +{ \ + ppc_vsr_t xt, xa, xb; \ + int i; \ + \ + getVSR(xA(opcode), &xa, env); \ + getVSR(xB(opcode), &xb, env); \ + getVSR(xT(opcode), &xt, env); \ + helper_reset_fpstatus(env); \ + \ + for (i = 0; i < nels; i++) { \ + if (unlikely((tp##_is_infinity(xa.fld[i]) && \ + tp##_is_zero(xb.fld[i])) || \ + (tp##_is_infinity(xb.fld[i]) && \ + tp##_is_zero(xa.fld[i])))) { \ + xt.fld[i] = float64_to_##tp( \ + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, \ + sfprf), \ + &env->fp_status); \ + } else { \ + if (unlikely(tp##_is_signaling_nan(xa.fld[i]) || \ + tp##_is_signaling_nan(xb.fld[i]))) { \ + fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf); \ + } \ + xt.fld[i] = tp##_mul(xa.fld[i], xb.fld[i], &env->fp_status); \ + if (sfprf) { \ + helper_compute_fprf(env, xt.fld[i], sfprf); \ + } \ + } \ + } \ + \ + putVSR(xT(opcode), &xt, env); \ + helper_float_check_status(env); \ +} + +VSX_MUL(xsmuldp, 1, float64, f64, 1) +VSX_MUL(xvmuldp, 2, float64, f64, 0) +VSX_MUL(xvmulsp, 4, float32, f32, 0) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 98b0bc5..a76b159 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -253,12 +253,15 @@ DEF_HELPER_4(vctsxs, void, env, avr, avr, i32) DEF_HELPER_2(xsadddp, void, env, i32) DEF_HELPER_2(xssubdp, void, env, i32) +DEF_HELPER_2(xsmuldp, void, env, i32) DEF_HELPER_2(xvadddp, void, env, i32) DEF_HELPER_2(xvsubdp, void, env, i32) +DEF_HELPER_2(xvmuldp, void, env, i32) DEF_HELPER_2(xvaddsp, void, env, i32) DEF_HELPER_2(xvsubsp, void, env, i32) +DEF_HELPER_2(xvmulsp, void, env, i32) DEF_HELPER_2(efscfsi, i32, env, i32) DEF_HELPER_2(efscfui, i32, env, i32) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d93bbf4..c743bf2 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7295,12 +7295,15 @@ static void gen_##name(DisasContext * ctx) \ GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX) #define VSX_LOGICAL(name, tcg_op) \ static void glue(gen_, name)(DisasContext * ctx) \ @@ -9986,12 +9989,15 @@ GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX), GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX), GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX), +GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX), GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), +GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX), GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX), GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX), +GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX), #undef VSX_LOGICAL #define VSX_LOGICAL(name, opc2, opc3, fl2) \