From patchwork Fri Oct 11 13:07:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Musta X-Patchwork-Id: 282750 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 008E12C007E for ; Sat, 12 Oct 2013 00:08:42 +1100 (EST) Received: from localhost ([::1]:54280 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VUcSN-0004Fq-6n for incoming@patchwork.ozlabs.org; Fri, 11 Oct 2013 09:08:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41330) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VUcRl-0003jo-QU for qemu-devel@nongnu.org; Fri, 11 Oct 2013 09:08:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VUcRd-0001R1-7u for qemu-devel@nongnu.org; Fri, 11 Oct 2013 09:08:01 -0400 Received: from mail-qe0-x236.google.com ([2607:f8b0:400d:c02::236]:41403) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VUcRM-0001Np-80; Fri, 11 Oct 2013 09:07:36 -0400 Received: by mail-qe0-f54.google.com with SMTP id 1so3290202qec.13 for ; Fri, 11 Oct 2013 06:07:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=Pbnj/nZvJDgM3krfJsQKzWEA5Ytw1KGTbIgGCNKwNcU=; b=MJ/JzUFZxjQMhB/bQqFLBPtBT+KzKia2EezQ67gE8pujxijdtLR0bRT0/hZ8xRU0Gt Zof8GUn8i/h8gsIUTAmIXJeKPJVNSBLStDQhMK+auh4N4W2HS3ka2omgUrK9JK0MgcPT kCsdZkhK1rlpwsYOs11IIxmaHF6EhDL9R7f9959aPJ+2JOP+S2b1KJkCwN+fAxZCpct+ BB0CrkmlIqPn+FF5Xw57xCBIvBgkoPLZxjnp8+5OR/eWPXs4uSNNFfvvi3br4YUjcVYj jyzyY0jVqzMlufrh0ezrx3tmFYZxK9k+ZivvgaTUp4mZ6s9LT5+0REEnNbDcDjwdv9Zr FolA== X-Received: by 10.49.116.210 with SMTP id jy18mr7569415qeb.65.1381496855833; Fri, 11 Oct 2013 06:07:35 -0700 (PDT) Received: from [9.10.80.13] (rchp4.rochester.ibm.com. [129.42.161.36]) by mx.google.com with ESMTPSA id h6sm97120696qej.4.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 11 Oct 2013 06:07:35 -0700 (PDT) Message-ID: <5257F811.5070502@gmail.com> Date: Fri, 11 Oct 2013 08:07:29 -0500 From: Tom Musta User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 To: qemu-ppc@nongnu.org References: <5257F4DD.7000204@gmail.com> In-Reply-To: <5257F4DD.7000204@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c02::236 Cc: Tom Musta , qemu-devel@nongnu.org Subject: [Qemu-devel] [v2 12/13] Add xxspltw X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the VSX Splat Word (xxsplatw) instruction. This is the first instruction to use the UIM immediate field and consequently a decoder is also added. V2: reworked implementation per Richard Henderson's comments. Signed-off-by: Tom Musta --- target-ppc/translate.c | 31 +++++++++++++++++++++++++++++++ 1 files changed, 31 insertions(+), 0 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index fd34b93..a56b303 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -503,6 +503,7 @@ EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5); EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5); EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5); EXTRACT_HELPER(DM, 8, 2); +EXTRACT_HELPER(UIM, 16, 2); /*****************************************************************************/ /* PowerPC instructions table */ @@ -7366,6 +7367,35 @@ static void gen_xxsel(DisasContext * ctx) tcg_temp_free(c); } +static void gen_xxspltw(DisasContext *ctx) +{ + TCGv_i64 b, b2; + TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ? + cpu_vsrl(xB(ctx->opcode)) : + cpu_vsrh(xB(ctx->opcode)); + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + + b = tcg_temp_new(); + b2 = tcg_temp_new(); + + if (UIM(ctx->opcode) & 1) { + tcg_gen_ext32u_i64(b, vsr); + } else { + tcg_gen_shri_i64(b, vsr, 32); + } + + tcg_gen_shli_i64(b2, b, 32); + tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2); + tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); + + tcg_temp_free(b); + tcg_temp_free(b2); +} + /*** SPE extension ***/ /* Register moves */ @@ -9881,6 +9911,7 @@ VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX), VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX), GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), +GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), #define GEN_XXSEL_ROW(opc3) \ GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \