From patchwork Thu Jul 2 14:14:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Fedin X-Patchwork-Id: 490662 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6386A140081 for ; Fri, 3 Jul 2015 00:22:59 +1000 (AEST) Received: from localhost ([::1]:36889 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAfOD-0001IN-Ak for incoming@patchwork.ozlabs.org; Thu, 02 Jul 2015 10:22:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36685) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAfFq-0003lC-Qy for qemu-devel@nongnu.org; Thu, 02 Jul 2015 10:14:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZAfFl-0003Q0-RJ for qemu-devel@nongnu.org; Thu, 02 Jul 2015 10:14:18 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:32463) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZAfFl-0003Mc-KL for qemu-devel@nongnu.org; Thu, 02 Jul 2015 10:14:13 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NQV00BHA67N3TB0@mailout4.w1.samsung.com> for qemu-devel@nongnu.org; Thu, 02 Jul 2015 15:14:11 +0100 (BST) X-AuditID: cbfec7f5-f794b6d000001495-bd-55954732ae9d Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 02.81.05269.23745955; Thu, 2 Jul 2015 15:14:10 +0100 (BST) Received: from localhost ([106.109.131.169]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NQV008ZR67M5X60@eusync1.samsung.com>; Thu, 02 Jul 2015 15:14:10 +0100 (BST) From: Pavel Fedin To: qemu-devel@nongnu.org Date: Thu, 02 Jul 2015 17:14:01 +0300 Message-id: <513bf02212772ee3741d986d7d4625e1f2a1b454.1435844519.git.p.fedin@samsung.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-reply-to: References: In-reply-to: References: X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjluLIzCtJLcpLzFFi42I5/e/4ZV0j96mhBv8nWVnMOfOAxeJ47w4W i7bP39kdmD1ajrxl9bhzbQ+bx5Nrm5kCmKO4bFJSczLLUov07RK4Ml7edSjo0a9Y2HadqYHx mGoXIyeHhICJxNu2fjYIW0ziwr31QDYXh5DAUkaJif+fMEM43xglZr2eyAhSxSagLnH66wcW EFtEQFLid9dpsCJmgUlMEic3fgUbJSygKnH81TagIg4OFiD74wFDkDCvQLTE45kbobZpSCz6 MgfM5hQwl7j+tIkdxBYSMJM4eLONEZf4BEb+BYwMqxhFU0uTC4qT0nON9IoTc4tL89L1kvNz NzFCQunrDsalx6wOMQpwMCrx8K6omRIqxJpYVlyZe4hRgoNZSYR3i+XUUCHelMTKqtSi/Pii 0pzU4kOM0hwsSuK8M3e9DxESSE8sSc1OTS1ILYLJMnFwSjUwJn41q+BzXrfg3YZ9y2Tnt6j8 +r6tc67Z4Yya5t8+u24vtHidauE1aX1fluuMh/lHorY/qQuuYcy4+yP+6fuMl6ZLOYTyXVv2 CxzoFVGMWOm8wKNRcsaXKetS0r+LV+flHfSLP9UsveGggt6SBJ8N+6s77Blr4jd8u5QQ/a/d bi1fmJHStHo/JZbijERDLeai4kQArtkssSECAAA= X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 210.118.77.14 Cc: Peter Maydell , Shlomo Pongratz , Shlomo Pongratz , Christoffer Dall , Eric Auger Subject: [Qemu-devel] [PATCH v4 3/9] GICv3 support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Shlomo Pongratz Add system instructions used by the Linux (kernel) GICv3 device driver Signed-off-by: Shlomo Pongratz --- target-arm/cpu.h | 12 ++++++ target-arm/cpu64.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 117 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 80297b3..c04b54c 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1024,6 +1024,18 @@ void armv7m_nvic_set_pending(void *opaque, int irq); int armv7m_nvic_acknowledge_irq(void *opaque); void armv7m_nvic_complete_irq(void *opaque, int irq); +void armv8_gicv3_set_sgi(void *opaque, int cpuindex, uint64_t value); +uint64_t armv8_gicv3_acknowledge_irq(void *opaque, int cpuindex, + MemTxAttrs attrs); +void armv8_gicv3_complete_irq(void *opaque, int cpuindex, int irq, + MemTxAttrs attrs); +uint64_t armv8_gicv3_get_priority_mask(void *opaque, int cpuindex); +void armv8_gicv3_set_priority_mask(void *opaque, int cpuindex, uint32_t mask); +uint64_t armv8_gicv3_get_sre(void *opaque); +void armv8_gicv3_set_sre(void *opaque, uint64_t sre); +uint64_t armv8_gicv3_get_igrpen1(void *opaque, int cpuindex); +void armv8_gicv3_set_igrpen1(void *opaque, int cpuindex, uint64_t igrpen1); + /* Interface for defining coprocessor registers. * Registers are defined in tables of arm_cp_reginfo structs * which are passed to define_arm_cp_regs(). diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 63c8b1c..7b0dee4 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -45,6 +45,72 @@ static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) } #endif +#ifndef CONFIG_USER_ONLY +static void sgi_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + CPUState *cpu = ENV_GET_CPU(env); + armv8_gicv3_set_sgi(env->nvic, cpu->cpu_index, value); +} + +static uint64_t iar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t value; + MemTxAttrs attrs;; + CPUState *cpu = ENV_GET_CPU(env); + attrs.secure = arm_is_secure_below_el3(env) ? 1 : 0; + value = armv8_gicv3_acknowledge_irq(env->nvic, cpu->cpu_index, attrs); + return value; +} + +static void sre_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + armv8_gicv3_set_sre(env->nvic, value); +} + +static uint64_t sre_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t value; + value = armv8_gicv3_get_sre(env->nvic); + return value; +} + +static void eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + MemTxAttrs attrs; + CPUState *cpu = ENV_GET_CPU(env); + attrs.secure = arm_is_secure_below_el3(env) ? 1 : 0; + armv8_gicv3_complete_irq(env->nvic, cpu->cpu_index, value, attrs); +} + +static uint64_t pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t value; + CPUState *cpu = ENV_GET_CPU(env); + value = armv8_gicv3_get_priority_mask(env->nvic, cpu->cpu_index); + return value; +} + +static void pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + CPUState *cpu = ENV_GET_CPU(env); + armv8_gicv3_set_priority_mask(env->nvic, cpu->cpu_index, value); +} + +static uint64_t igrpen1_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t value; + CPUState *cpu = ENV_GET_CPU(env); + value = armv8_gicv3_get_igrpen1(env->nvic, cpu->cpu_index); + return value; +} + +static void igrpen1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + CPUState *cpu = ENV_GET_CPU(env); + armv8_gicv3_set_igrpen1(env->nvic, cpu->cpu_index, value); +} +#endif + static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = { #ifndef CONFIG_USER_ONLY { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, @@ -89,6 +155,45 @@ static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = { { .name = "L2MERRSR", .cp = 15, .opc1 = 3, .crm = 15, .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, + { .name = "EIOR1_EL1", .state = ARM_CP_STATE_AA64, +#ifndef CONFIG_USER_ONLY + .writefn = eoir_write, +#endif + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "IAR1_EL1", .state = ARM_CP_STATE_AA64, +#ifndef CONFIG_USER_ONLY + .readfn = iar_read, +#endif + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 0, + .access = PL1_R, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "SGI1R_EL1", .state = ARM_CP_STATE_AA64, +#ifndef CONFIG_USER_ONLY + .writefn = sgi_write, +#endif + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5, + .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "PMR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0, +#ifndef CONFIG_USER_ONLY + .readfn = pmr_read, .writefn = pmr_write, +#endif + .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "CTLR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, + .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "SRE_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 5, .resetvalue = 0, +#ifndef CONFIG_USER_ONLY + .readfn = sre_read, .writefn = sre_write, +#endif + .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "IGRPEN1_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7, +#ifndef CONFIG_USER_ONLY + .readfn = igrpen1_read, .writefn = igrpen1_write, +#endif + .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, REGINFO_SENTINEL };