From patchwork Mon Jun 1 18:04:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 479123 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 03BA61412EA for ; Tue, 2 Jun 2015 04:05:07 +1000 (AEST) Received: from localhost ([::1]:53728 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU5B-0003sA-09 for incoming@patchwork.ozlabs.org; Mon, 01 Jun 2015 14:05:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU4V-0002lF-UO for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzU4R-0008Cp-Sp for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:23 -0400 Received: from mail-ob0-f181.google.com ([209.85.214.181]:34227) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU4R-0008Ck-OQ for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:19 -0400 Received: by obew15 with SMTP id w15so110070641obe.1 for ; Mon, 01 Jun 2015 11:04:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=qgaNWFhPC+mOWVag7Cgb3AUjCnuJ0z0CJvlLoi5OuOQ=; b=E38qB3uIqv8hPVl4j7MEZ64nZTfpCUqzjpNB9ImPyussc+lrPue2lufp2Cd7gvARP3 D63MM82lLfYBCmO3SruT2Hk1FYvogYudpJQymeD4QDU2Qnzn7IRRa5wTIYQ2NxdY2CEZ QXhWZzhIreCqVgx6aJo4L6F11wDkO4gUQwxkfTbwkBkMUA34NxX2dTIX+JJoSGgBsy8m 30Iiy0LU+Pap0R406Xdc9DKbHBr0P1wpZF9ck1LYsrGBr+lbp/fui6X08PbR4OUwN1Eb aFBDB3Okq+aABSbCr67F5fgDEgG5OTjcUObcpXobdXT/rAUf9siZ+TEX2i180dlyFQqI u73w== X-Gm-Message-State: ALoCoQmzLL5/xnUZ3JULMAcTp5ZicVhHd2fRtCztEMOtYmcOivLM0E2GRY8XTxP1Fl8uOBgya8Cp X-Received: by 10.60.74.2 with SMTP id p2mr19101728oev.57.1433181859382; Mon, 01 Jun 2015 11:04:19 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id x77sm8007237oix.24.2015.06.01.11.04.18 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Jun 2015 11:04:19 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Mon, 1 Jun 2015 11:04:17 -0700 Message-Id: <404697de2b76ec7deadc1d8181cae98e8bdb1f07.1433180153.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 2.4.2.3.g2ffcb72 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.181 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, zach.pfeffer@xilinx.com, jues@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v1 2/9] arm: helper: Factor out CP regs common to [pv]msa X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org V6+ PMSA and VMSA share some common registers that are currently in the VMSA definition block. Split them out into a new def that can be shared to PMSA. Signed-off-by: Peter Crosthwaite --- target-arm/helper.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 1cc4993..78b6406 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1846,7 +1846,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } -static const ARMCPRegInfo vmsa_cp_reginfo[] = { +static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_ALIAS, .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), @@ -1856,6 +1856,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .access = PL1_RW, .resetvalue = 0, .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, + { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, + .access = PL1_RW, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), + offsetof(CPUARMState, cp15.dfar_ns) } }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, .access = PL1_RW, @@ -1884,10 +1892,6 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), .resetvalue = 0, }, - { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, - .access = PL1_RW, .resetvalue = 0, - .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), - offsetof(CPUARMState, cp15.dfar_ns) } }, REGINFO_SENTINEL }; @@ -3279,6 +3283,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) assert(!arm_feature(env, ARM_FEATURE_V6)); define_arm_cp_regs(cpu, pmsav5_cp_reginfo); } else { + define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {