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28 Oct 2020 07:38:58 -0700 IronPort-SDR: zzoOC2sZNKh9S/ZA3v3cgCTF6zN0aIqRqydjTLlcGjXnGQRYuxp0pPQkn/a4f4x3nSZHfhDrrw Dh4Sr3sZGkhDhi5iomAq+h1RsMAU3e/6OLKbcMrIPOkVqLHqHzX/wiw+YrO8wIHTtY6OqnuUMY a0BaQVDwS4tqs1Ah1YZNjFYpzIuMOnXBFjpHT9qp1VuATcmkO0U6fs+t+92ZHBKvgYMT3B2wjf 5iEbUO+gLQFPym/he3xm1XflWCrLO2DTostM03jjtq+kTM9F0J2IRQqX0wDa3Eo9XECFWBkYgj q1w= WDCIronportException: Internal Received: from usa003000.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.131]) by uls-op-cesaip01.wdc.com with ESMTP; 28 Oct 2020 07:53:48 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Date: Wed, 28 Oct 2020 07:42:23 -0700 Message-Id: <3f5666c9eb72758011c14a660de99ba86a0b6561.1603896075.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=563b96974=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/28 10:53:43 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, richard.henderson@linaro.org, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When performing the hypervisor load/store operations set the MMU mode to indicate that we are virtualised. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/op_helper.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e20d56dcb8..548c5851ec 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -235,30 +235,31 @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { target_ulong pte; + int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK; riscv_cpu_set_two_stage_lookup(env, true); switch (memop) { case MO_SB: - pte = cpu_ldsb_data_ra(env, address, GETPC()); + pte = cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_UB: - pte = cpu_ldub_data_ra(env, address, GETPC()); + pte = cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TESW: - pte = cpu_ldsw_data_ra(env, address, GETPC()); + pte = cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUW: - pte = cpu_lduw_data_ra(env, address, GETPC()); + pte = cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TESL: - pte = cpu_ldl_data_ra(env, address, GETPC()); + pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUL: - pte = cpu_ldl_data_ra(env, address, GETPC()); + pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEQ: - pte = cpu_ldq_data_ra(env, address, GETPC()); + pte = cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC()); break; default: g_assert_not_reached(); @@ -284,23 +285,25 @@ void helper_hyp_store(CPURISCVState *env, target_ulong address, (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { + int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK; + riscv_cpu_set_two_stage_lookup(env, true); switch (memop) { case MO_SB: case MO_UB: - cpu_stb_data_ra(env, address, val, GETPC()); + cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TESW: case MO_TEUW: - cpu_stw_data_ra(env, address, val, GETPC()); + cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TESL: case MO_TEUL: - cpu_stl_data_ra(env, address, val, GETPC()); + cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TEQ: - cpu_stq_data_ra(env, address, val, GETPC()); + cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; default: g_assert_not_reached(); @@ -326,15 +329,16 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { target_ulong pte; + int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK; riscv_cpu_set_two_stage_lookup(env, true); switch (memop) { case MO_TEUW: - pte = cpu_lduw_data_ra(env, address, GETPC()); + pte = cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUL: - pte = cpu_ldl_data_ra(env, address, GETPC()); + pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; default: g_assert_not_reached();