From patchwork Fri Nov 12 09:51:40 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 70946 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 32A2BB7126 for ; Fri, 12 Nov 2010 20:58:04 +1100 (EST) Received: from localhost ([127.0.0.1]:52026 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGqOD-0005rR-Vt for incoming@patchwork.ozlabs.org; Fri, 12 Nov 2010 04:57:50 -0500 Received: from [140.186.70.92] (port=44943 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGqIN-00032f-4S for qemu-devel@nongnu.org; Fri, 12 Nov 2010 04:51:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PGqIL-0001Hr-H7 for qemu-devel@nongnu.org; Fri, 12 Nov 2010 04:51:47 -0500 Received: from mail.valinux.co.jp ([210.128.90.3]:33353) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PGqIL-0001HL-2D for qemu-devel@nongnu.org; Fri, 12 Nov 2010 04:51:45 -0500 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id B98D487494; Fri, 12 Nov 2010 18:51:42 +0900 (JST) Received: (nullmailer pid 26939 invoked by uid 1000); Fri, 12 Nov 2010 09:51:42 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Fri, 12 Nov 2010 18:51:40 +0900 Message-Id: <3ef71132cd5982a2afdff8089126f2c3ad8f759b.1289555375.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: yamahata@valinux.co.jp, mst@redhat.com Subject: [Qemu-devel] [PATCH 2/4] pci: clean up pci command register io/memory bit initialization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch fixes the initialization of io/memory bit of command register. Those bits for type 1 device is RW. Those bits for type 0 device is RO = 0 if it has no io/memory BAR RW if it has io/memory BAR Signed-off-by: Isaku Yamahata --- hw/pci.c | 20 +++++++++++++++++--- 1 files changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 86900a2..a734e14 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -644,10 +644,14 @@ static void pci_init_wmask(PCIDevice *dev) /* * bit 0: PCI_COMMAND_IO * type 0: if IO BAR is used, RW - * type 1: RW + * This is handled by pci_register_bar() + * type 1: RW: + * This is fixed by pci_init_wmask_bridge() * bit 1: PCI_COMMAND_MEMORY * type 0: if IO BAR is used, RW + * This is handled by pci_register_bar() * type 1: RW + * This is fixed by pci_init_wmask_bridge() * bit 2: PCI_COMMAND_MASTER * type 0: RW if bus master * type 1: RW @@ -682,8 +686,7 @@ static void pci_init_wmask(PCIDevice *dev) * bit 11-15: reserved */ pci_set_word(dev->wmask + PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR | + PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_INTX_DISABLE); memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, @@ -692,6 +695,9 @@ static void pci_init_wmask(PCIDevice *dev) static void pci_init_wmask_bridge(PCIDevice *d) { + pci_word_test_and_set_mask(d->wmask + PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and PCI_SEC_LETENCY_TIMER */ memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); @@ -929,6 +935,14 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, if (region_num == PCI_ROM_SLOT) { /* ROM enable bit is writeable */ wmask |= PCI_ROM_ADDRESS_ENABLE; + } else { + if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { + pci_word_test_and_set_mask(pci_dev->wmask + PCI_COMMAND, + PCI_COMMAND_IO); + } else { + pci_word_test_and_set_mask(pci_dev->wmask + PCI_COMMAND, + PCI_COMMAND_MEMORY); + } } pci_set_long(pci_dev->config + addr, type); if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&