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Mon, 23 Mar 2015 04:05:14 -0700 Received: from xsj-tvapsmtp02 (xsj-tvapsmtp02.xilinx.com [172.16.1.203]) by tsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id t2NB1L6v014872; Mon, 23 Mar 2015 04:01:22 -0700 Received: from [172.19.74.49] (port=60776 helo=xsjsorenbubuntu.xilinx.com) by xsj-tvapsmtp02 with esmtp (Exim 4.63) (envelope-from ) id 1Ya0AT-0006bT-A9; Mon, 23 Mar 2015 04:05:13 -0700 From: Peter Crosthwaite To: Date: Mon, 23 Mar 2015 04:05:13 -0700 Message-ID: <3e026b514473978a9a68cf272a24a52c30bed437.1427108387.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 2.3.1.2.g90df61e.dirty In-Reply-To: References: X-RCIS-Action: ALLOW X-TM-AS-MML: disable X-TM-AS-Product-Ver: IMSS-7.1.0.1679-7.5.0.1018-21418.005 X-TM-AS-Result: No--6.559-7.0-31-10 X-imss-scan-details: No--6.559-7.0-31-10 X-TMASE-MatchedRID: gb+vm/q4Wbx37FC663+5p1z+axQLnAVBQPCWRE0Lo8IXGHD9U1OuR/2B QpWTK4KNjBDXS4YxDzSgGOZ3m2LY56epdpfrXbSjuIwLnB3Aqp2WHGENdT+VP2PZr2NA6vZGc9r DOIgOR4NMY5EyqZygDOXVY6vvRRzfdT7rfTiuL8XYd2+/8wYTda19jpg9rDdhPPNQscfVdONhiF 7nvrCz3YVZhfZM9sMS4YDO5a1ajtgdiedB1vHs3khwlOfYeSqxm/y00tE9StZ+YesuCgkiXPmv8 3Rzid1pQf+k9Hlgs/2A73Z+pBAiajcpdZ3fQiLdFEUknJ/kEl7dB/CxWTRRu25FeHtsUoHu9jYx KMT4p9fFNtlsb+iRbL74YEStHh8e7PLytVjF22g2RRIMOrvjaQ== X-EOPAttributedMessage: 0 Received-SPF: Fail (protection.outlook.com: domain of xilinx.com does not designate 149.199.60.96 as permitted sender) receiver=protection.outlook.com; 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PCL:0; RULEID:(601004)(5002010)(5005006); SRVR:BY2FFO11HUB014; BCL:0; PCL:0; RULEID:; SRVR:BY2FFO11HUB014; X-Forefront-PRVS: 05245CA661 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2015 11:05:14.9181 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.96]; Helo=[xsj-tvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2FFO11HUB014 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 X-Received-From: 157.56.111.81 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, ozaki.ryota@gmail.com, michals@xilinx.com, zach.pfeffer@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v4 04/16] arm: Introduce Xilinx ZynqMP SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org With quad Cortex-A53 CPUs. Signed-off-by: Peter Crosthwaite Reviewed-by: Alistair Francis --- changed since v2: Added [*] to cpu child property name. changed since v1: Add &error_abort to CPU child adder call. default-configs/aarch64-softmmu.mak | 2 +- hw/arm/Makefile.objs | 1 + hw/arm/xlnx-zynqmp.c | 72 +++++++++++++++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 21 +++++++++++ 4 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 hw/arm/xlnx-zynqmp.c create mode 100644 include/hw/arm/xlnx-zynqmp.h diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak index 6d3b5c7..96dd994 100644 --- a/default-configs/aarch64-softmmu.mak +++ b/default-configs/aarch64-softmmu.mak @@ -3,4 +3,4 @@ # We support all the 32 bit boards so need all their config include arm-softmmu.mak -# Currently no 64-bit specific config requirements +CONFIG_XLNX_ZYNQMP=y diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 2577f68..d7cd5f4 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -10,3 +10,4 @@ obj-$(CONFIG_DIGIC) += digic.o obj-y += omap1.o omap2.o strongarm.o obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o +obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c new file mode 100644 index 0000000..41c207a --- /dev/null +++ b/hw/arm/xlnx-zynqmp.c @@ -0,0 +1,72 @@ +/* + * Xilinx Zynq MPSoC emulation + * + * Copyright (C) 2015 Xilinx Inc + * Written by Peter Crosthwaite + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "hw/arm/xlnx-zynqmp.h" + +static void xlnx_zynqmp_init(Object *obj) +{ + XlnxZynqMPState *s = XLNX_ZYNQMP(obj); + int i; + + for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { + object_initialize(&s->cpu[i], sizeof(s->cpu[i]), + "cortex-a53-" TYPE_ARM_CPU); + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), + &error_abort); + } +} + +#define ERR_PROP_CHECK_RETURN(err, errp) do { \ + if (err) { \ + error_propagate((errp), (err)); \ + return; \ + } \ +} while (0) + +static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) +{ + XlnxZynqMPState *s = XLNX_ZYNQMP(dev); + uint8_t i; + Error *err = NULL; + + for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) { + object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err); + ERR_PROP_CHECK_RETURN(err, errp); + } +} + +static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = xlnx_zynqmp_realize; +} + +static const TypeInfo xlnx_zynqmp_type_info = { + .name = TYPE_XLNX_ZYNQMP, + .parent = TYPE_DEVICE, + .instance_size = sizeof(XlnxZynqMPState), + .instance_init = xlnx_zynqmp_init, + .class_init = xlnx_zynqmp_class_init, +}; + +static void xlnx_zynqmp_register_types(void) +{ + type_register_static(&xlnx_zynqmp_type_info); +} + +type_init(xlnx_zynqmp_register_types) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h new file mode 100644 index 0000000..d6b3b92 --- /dev/null +++ b/include/hw/arm/xlnx-zynqmp.h @@ -0,0 +1,21 @@ +#ifndef XLNX_ZYNQMP_H_ + +#include "qemu-common.h" +#include "hw/arm/arm.h" + +#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" +#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ + TYPE_XLNX_ZYNQMP) + +#define XLNX_ZYNQMP_NUM_CPUS 4 + +typedef struct XlnxZynqMPState { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + + ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS]; +} XlnxZynqMPState; + +#define XLNX_ZYNQMP_H_ +#endif