From patchwork Tue Dec 3 07:00:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 296090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F0D2D2C00A0 for ; Tue, 3 Dec 2013 18:01:56 +1100 (EST) Received: from localhost ([::1]:40464 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnjzW-0003Ul-Km for incoming@patchwork.ozlabs.org; Tue, 03 Dec 2013 02:01:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50307) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vnjyz-0003I4-Fj for qemu-devel@nongnu.org; Tue, 03 Dec 2013 02:01:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vnjyq-00066M-Bk for qemu-devel@nongnu.org; Tue, 03 Dec 2013 02:01:21 -0500 Received: from mail-pd0-f175.google.com ([209.85.192.175]:59171) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vnjyq-00066G-3J for qemu-devel@nongnu.org; Tue, 03 Dec 2013 02:01:12 -0500 Received: by mail-pd0-f175.google.com with SMTP id w10so19644306pde.34 for ; Mon, 02 Dec 2013 23:01:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=lRSwdqKpGHvtnPp+IRKfsbkv+FupsvAtL4lvD6/1ogM=; b=LehY3eCxzREYdGz1voux/078LunGLzOpAKuOTSYIRFYHbb8eU/qFoM4zxyY3YLAWMj /aAgZp2EjzK2u1fbPrcjCSRtMylwYunq6+04E02DVw2fdb1VvIwfrrYOYI52l0MdNNNv zKp/EzFk/fr0x3qHtK1IO7iekRqAt7sg3TVE+0fPFqgWKLgsqoWOEIEEG5RqFrOcYtMA BZaqM1nxOcA6s6z5wGXBJrKFM3fjl/oFIMuxV3pNFes3/Rnuvt7PFDX84CoG3nNn2e0Q yhW8nxKpK2pbNlkuPJdnKxamkVpOspE49fmgRvZpx6THITmwKCTkwvzd5+HdCJioJGmx oL6A== X-Gm-Message-State: ALoCoQmOf8uMxMoWznULQRe+EGjIMKbhCQZ5qH0ycHEHEUQQN9DnLo092uvkV6YqiE1GQMzJFBcs X-Received: by 10.68.190.33 with SMTP id gn1mr36954320pbc.48.1386054071307; Mon, 02 Dec 2013 23:01:11 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id pl1sm127582905pbb.20.2013.12.02.23.01.10 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 02 Dec 2013 23:01:10 -0800 (PST) From: Peter Crosthwaite To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Mon, 2 Dec 2013 23:00:39 -0800 Message-Id: <2d8e428867da815b6164b59bc46eaf28d6f76590.1386053678.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.8.4.4 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.175 Cc: peter.crosthwaite@xilinx.com, afaerber@suse.de, mark.langsdorf@calxeda.com Subject: [Qemu-devel] [PATCH arm-devs v3 3/9] target-arm: Define and use ARM_FEATURE_CBAR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Some processors (notably A9 within Highbank) define and use the CP15 configuration base address (CBAR). This is vendor specific so its best implemented as a CPU property (otherwise we would need vendor specific child classes for every ARM implementation). This patch prepares support for converting CBAR reset value to a CPU property by moving the CP registration out of the CPU init fn, as registration will need to happen at realize time to pick up any property updates. The easiest way to do this is via definition of a new ARM_FEATURE to flag the existence of the register. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell --- changed since v2: msg typo: existence Enable CBAR for a15 as well target-arm/cpu.c | 12 +++--------- target-arm/cpu.h | 1 + target-arm/helper.c | 9 +++++++++ 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index d40f2a7..90413ee 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -590,6 +590,7 @@ static void cortex_a9_initfn(Object *obj) * and valid configurations; we don't model A9UP). */ set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_CBAR); cpu->midr = 0x410fc090; cpu->reset_fpsid = 0x41033090; cpu->mvfr0 = 0x11110222; @@ -612,15 +613,7 @@ static void cortex_a9_initfn(Object *obj) cpu->clidr = (1 << 27) | (1 << 24) | 3; cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ - { - ARMCPRegInfo cbar = { - .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, - .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, - .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) - }; - define_one_arm_cp_reg(cpu, &cbar); - define_arm_cp_regs(cpu, cortexa9_cp_reginfo); - } + define_arm_cp_regs(cpu, cortexa9_cp_reginfo); } #ifndef CONFIG_USER_ONLY @@ -657,6 +650,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR); set_feature(&cpu->env, ARM_FEATURE_LPAE); cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 9f110f1..859750a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -461,6 +461,7 @@ enum arm_features { ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ + ARM_FEATURE_CBAR, /* has cp15 CBAR */ ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ ARM_FEATURE_V8, diff --git a/target-arm/helper.c b/target-arm/helper.c index 587ff49..59b59c7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1745,6 +1745,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &auxcr); } + if (arm_feature(env, ARM_FEATURE_CBAR)) { + ARMCPRegInfo cbar = { + .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, + .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, + .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address) + }; + define_one_arm_cp_reg(cpu, &cbar); + } + /* Generic registers whose values depend on the implementation */ { ARMCPRegInfo sctlr = {