diff mbox

[v3,5/7] acpi:cpu hotplug: set pcmachine as icc bus' hotplug handler

Message ID 2834a1eb30e4071523eb774b40d30f2d73b6c079.1421214155.git.zhugh.fnst@cn.fujitsu.com
State New
Headers show

Commit Message

Zhu Guihua Jan. 14, 2015, 7:27 a.m. UTC
From: Gu Zheng <guz.fnst@cn.fujitsu.com>

As the pre-check in the qdev_device_add():
    if (qdev_hotplug && bus && !qbus_is_hotpluggable(bus)) {
        qerror_report(QERR_BUS_NO_HOTPLUG, bus->name);
        return NULL;
    }
if device has parent bus, the bus must have valid hotplug_handler,
otherwise can not hot plug.
Currently cpu hotplug is based on the PCMachine's hotplug handler,
so when hot add cpu, the hotpluggable check of icc bus will be
rejected.
So we set pcmachine as icc bus' hotplug handler to avoid the rejetion.

Signed-off-by: Gu Zheng <guz.fnst@cn.fujitsu.com>
Signed-off-by: Zhu Guihua <zhugh.fnst@cn.fujitsu.com>
---
 hw/cpu/icc_bus.c         | 5 +++++
 hw/i386/pc_piix.c        | 5 +++++
 hw/i386/pc_q35.c         | 5 +++++
 include/hw/cpu/icc_bus.h | 2 ++
 4 files changed, 17 insertions(+)

Comments

Igor Mammedov Jan. 29, 2015, 2:18 p.m. UTC | #1
On Wed, 14 Jan 2015 15:27:28 +0800
Zhu Guihua <zhugh.fnst@cn.fujitsu.com> wrote:

> From: Gu Zheng <guz.fnst@cn.fujitsu.com>
> 
> As the pre-check in the qdev_device_add():
>     if (qdev_hotplug && bus && !qbus_is_hotpluggable(bus)) {
>         qerror_report(QERR_BUS_NO_HOTPLUG, bus->name);
>         return NULL;
>     }
> if device has parent bus, the bus must have valid hotplug_handler,
> otherwise can not hot plug.
> Currently cpu hotplug is based on the PCMachine's hotplug handler,
> so when hot add cpu, the hotpluggable check of icc bus will be
> rejected.
> So we set pcmachine as icc bus' hotplug handler to avoid the rejetion.
ICC bus was invented only to provide hotplug capability to
CPU and APIC because at the time being hotplug was available only for
BUS attached devices.

Could we drop ICC bus impl. completely and switch to bus-less
CPU+APIC hotplug, handling them in the same manner as pc-dimm?

> 
> Signed-off-by: Gu Zheng <guz.fnst@cn.fujitsu.com>
> Signed-off-by: Zhu Guihua <zhugh.fnst@cn.fujitsu.com>
> ---
>  hw/cpu/icc_bus.c         | 5 +++++
>  hw/i386/pc_piix.c        | 5 +++++
>  hw/i386/pc_q35.c         | 5 +++++
>  include/hw/cpu/icc_bus.h | 2 ++
>  4 files changed, 17 insertions(+)
> 
> diff --git a/hw/cpu/icc_bus.c b/hw/cpu/icc_bus.c
> index 6646ea2..f455a20 100644
> --- a/hw/cpu/icc_bus.c
> +++ b/hw/cpu/icc_bus.c
> @@ -92,6 +92,11 @@ static void icc_bridge_init(Object *obj)
>      s->icc_bus.apic_address_space = &s->apic_container;
>  }
>  
> +ICCBus *get_icc_bus(DeviceState *dev)
> +{
> +    return &ICC_BRIDGE(dev)->icc_bus;
> +}
> +
>  static void icc_bridge_class_init(ObjectClass *oc, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(oc);
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index f0a3201..363f796 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -281,6 +281,7 @@ static void pc_init1(MachineState *machine,
>      if (pci_enabled && acpi_enabled) {
>          DeviceState *piix4_pm;
>          I2CBus *smbus;
> +        ICCBus *iccbus;
>  
>          smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
>          /* TODO: Populate SPD eeprom data.  */
> @@ -296,6 +297,10 @@ static void pc_init1(MachineState *machine,
>                                   OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
>          object_property_set_link(OBJECT(machine), OBJECT(piix4_pm),
>                                   PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
> +
> +        iccbus = get_icc_bus(icc_bridge);
> +        object_property_set_link(OBJECT(iccbus), OBJECT(pc_machine),
> +                                 QDEV_HOTPLUG_HANDLER_PROPERTY, &error_abort);
>      }
>  
>      if (pci_enabled) {
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index a432944..2ce8b70 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -88,6 +88,7 @@ static void pc_q35_init(MachineState *machine)
>      PcGuestInfo *guest_info;
>      ram_addr_t lowmem;
>      DriveInfo *hd[MAX_SATA_PORTS];
> +    ICCBus *iccbus;
>  
>      /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
>       * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
> @@ -212,6 +213,10 @@ static void pc_q35_init(MachineState *machine)
>      object_property_set_link(OBJECT(machine), OBJECT(lpc),
>                               PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
>  
> +    iccbus = get_icc_bus(icc_bridge);
> +    object_property_set_link(OBJECT(iccbus), OBJECT(pc_machine),
> +                             QDEV_HOTPLUG_HANDLER_PROPERTY, &error_abort);
> +
>      ich9_lpc = ICH9_LPC_DEVICE(lpc);
>      ich9_lpc->pic = gsi;
>      ich9_lpc->ioapic = gsi_state->ioapic_irq;
> diff --git a/include/hw/cpu/icc_bus.h b/include/hw/cpu/icc_bus.h
> index 98a979f..7e53afb 100644
> --- a/include/hw/cpu/icc_bus.h
> +++ b/include/hw/cpu/icc_bus.h
> @@ -44,6 +44,8 @@ typedef struct ICCBus {
>  
>  #define ICC_BUS(obj) OBJECT_CHECK(ICCBus, (obj), TYPE_ICC_BUS)
>  
> +ICCBus *get_icc_bus(DeviceState *dev);
> +
>  /**
>   * ICCDevice:
>   *
diff mbox

Patch

diff --git a/hw/cpu/icc_bus.c b/hw/cpu/icc_bus.c
index 6646ea2..f455a20 100644
--- a/hw/cpu/icc_bus.c
+++ b/hw/cpu/icc_bus.c
@@ -92,6 +92,11 @@  static void icc_bridge_init(Object *obj)
     s->icc_bus.apic_address_space = &s->apic_container;
 }
 
+ICCBus *get_icc_bus(DeviceState *dev)
+{
+    return &ICC_BRIDGE(dev)->icc_bus;
+}
+
 static void icc_bridge_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index f0a3201..363f796 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -281,6 +281,7 @@  static void pc_init1(MachineState *machine,
     if (pci_enabled && acpi_enabled) {
         DeviceState *piix4_pm;
         I2CBus *smbus;
+        ICCBus *iccbus;
 
         smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
         /* TODO: Populate SPD eeprom data.  */
@@ -296,6 +297,10 @@  static void pc_init1(MachineState *machine,
                                  OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
         object_property_set_link(OBJECT(machine), OBJECT(piix4_pm),
                                  PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
+
+        iccbus = get_icc_bus(icc_bridge);
+        object_property_set_link(OBJECT(iccbus), OBJECT(pc_machine),
+                                 QDEV_HOTPLUG_HANDLER_PROPERTY, &error_abort);
     }
 
     if (pci_enabled) {
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index a432944..2ce8b70 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -88,6 +88,7 @@  static void pc_q35_init(MachineState *machine)
     PcGuestInfo *guest_info;
     ram_addr_t lowmem;
     DriveInfo *hd[MAX_SATA_PORTS];
+    ICCBus *iccbus;
 
     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
@@ -212,6 +213,10 @@  static void pc_q35_init(MachineState *machine)
     object_property_set_link(OBJECT(machine), OBJECT(lpc),
                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 
+    iccbus = get_icc_bus(icc_bridge);
+    object_property_set_link(OBJECT(iccbus), OBJECT(pc_machine),
+                             QDEV_HOTPLUG_HANDLER_PROPERTY, &error_abort);
+
     ich9_lpc = ICH9_LPC_DEVICE(lpc);
     ich9_lpc->pic = gsi;
     ich9_lpc->ioapic = gsi_state->ioapic_irq;
diff --git a/include/hw/cpu/icc_bus.h b/include/hw/cpu/icc_bus.h
index 98a979f..7e53afb 100644
--- a/include/hw/cpu/icc_bus.h
+++ b/include/hw/cpu/icc_bus.h
@@ -44,6 +44,8 @@  typedef struct ICCBus {
 
 #define ICC_BUS(obj) OBJECT_CHECK(ICCBus, (obj), TYPE_ICC_BUS)
 
+ICCBus *get_icc_bus(DeviceState *dev);
+
 /**
  * ICCDevice:
  *