@@ -267,7 +267,7 @@ static const TCGCPUOps alpha_tcg_ops = {
.cpu_exec_interrupt = alpha_cpu_exec_interrupt,
.cpu_exec_halt = alpha_cpu_has_work,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = alpha_cpu_do_interrupt,
+ .do_interrupt = alpha_cpu_do_interrupt,
.do_transaction_failed = alpha_cpu_do_transaction_failed,
.do_unaligned_access = alpha_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
@@ -26,6 +26,7 @@
#include "fpu/softfloat-types.h"
#include "fpu/softfloat-helpers.h"
#include "exec/helper-proto.h"
+#include "qemu/main-loop.h"
#include "qemu/qemu-print.h"
#include "system/memory.h"
#include "accel/tcg/cpu-loop.h"
@@ -341,6 +342,8 @@ void alpha_cpu_do_interrupt(CPUState *cs)
int i = cs->exception_index;
uint64_t last_pc = env->pc;
+ BQL_LOCK_GUARD();
+
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
const char *name = "<unknown>";
@@ -2606,7 +2606,7 @@ static const TCGCPUOps arm_tcg_ops = {
.cpu_exec_interrupt = arm_cpu_exec_interrupt,
.cpu_exec_halt = arm_cpu_exec_halt,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = arm_cpu_do_interrupt,
+ .do_interrupt = arm_cpu_do_interrupt,
.do_transaction_failed = arm_cpu_do_transaction_failed,
.do_unaligned_access = arm_cpu_do_unaligned_access,
.adjust_watchpoint_address = arm_adjust_watchpoint_address,
@@ -9714,6 +9714,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
uint64_t last_pc = cs->cc->get_pc(cs);
assert(!arm_feature(env, ARM_FEATURE_M));
+ BQL_LOCK_GUARD();
arm_log_exception(cs);
qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
@@ -304,7 +304,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = {
.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
.cpu_exec_halt = arm_cpu_exec_halt,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = arm_v7m_cpu_do_interrupt,
+ .do_interrupt = arm_v7m_cpu_do_interrupt,
.do_transaction_failed = arm_cpu_do_transaction_failed,
.do_unaligned_access = arm_cpu_do_unaligned_access,
.adjust_watchpoint_address = arm_adjust_watchpoint_address,
@@ -2214,6 +2214,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
bool ignore_stackfaults;
uint64_t last_pc = env->regs[15];
+ BQL_LOCK_GUARD();
+
arm_log_exception(cs);
/*
@@ -249,7 +249,7 @@ static const TCGCPUOps avr_tcg_ops = {
.cpu_exec_halt = avr_cpu_has_work,
.cpu_exec_reset = cpu_reset,
.tlb_fill = avr_cpu_tlb_fill,
- .do_interrupt_locked = avr_cpu_do_interrupt,
+ .do_interrupt = avr_cpu_do_interrupt,
/*
* TODO: code and data wrapping are different, but for the most part
* AVR only references bytes or aligned code fetches. But we use
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
+#include "qemu/main-loop.h"
#include "cpu.h"
#include "accel/tcg/cpu-ops.h"
#include "accel/tcg/cpu-loop.h"
@@ -89,6 +90,8 @@ void avr_cpu_do_interrupt(CPUState *cs)
vector = ctz64(env->intsrc) + 1;
}
+ BQL_LOCK_GUARD();
+
if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
do_stb(env, env->sp--, ret, 0);
do_stb(env, env->sp--, ret >> 8, 0);
@@ -272,7 +272,7 @@ static const TCGCPUOps hppa_tcg_ops = {
.cpu_exec_interrupt = hppa_cpu_exec_interrupt,
.cpu_exec_halt = hppa_cpu_has_work,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = hppa_cpu_do_interrupt,
+ .do_interrupt = hppa_cpu_do_interrupt,
.do_unaligned_access = hppa_cpu_do_unaligned_access,
.do_transaction_failed = hppa_cpu_do_transaction_failed,
#endif /* !CONFIG_USER_ONLY */
@@ -98,6 +98,8 @@ void hppa_cpu_do_interrupt(CPUState *cs)
uint64_t old_psw, old_gva_offset_mask;
uint64_t last_pc = cs->cc->get_pc(cs);
+ BQL_LOCK_GUARD();
+
/* As documented in pa2.0 -- interruption handling. */
/* step 1 */
env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env);
@@ -115,6 +115,8 @@ void x86_cpu_do_interrupt(CPUState *cs)
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
+ BQL_LOCK_GUARD();
+
if (cs->exception_index == EXCP_VMEXIT) {
assert(env->old_exception == -1);
do_vmexit(env);
@@ -179,7 +179,7 @@ const TCGCPUOps x86_tcg_ops = {
#else
.tlb_fill = x86_cpu_tlb_fill,
.pointer_wrap = x86_pointer_wrap,
- .do_interrupt_locked = x86_cpu_do_interrupt,
+ .do_interrupt = x86_cpu_do_interrupt,
.cpu_exec_halt = x86_cpu_exec_halt,
.cpu_exec_interrupt = x86_cpu_exec_interrupt,
.cpu_exec_reset = x86_cpu_exec_reset,
@@ -718,7 +718,7 @@ static const TCGCPUOps mips_tcg_ops = {
.cpu_exec_interrupt = mips_cpu_exec_interrupt,
.cpu_exec_halt = mips_cpu_has_work,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = mips_cpu_do_interrupt,
+ .do_interrupt = mips_cpu_do_interrupt,
.do_transaction_failed = mips_cpu_do_transaction_failed,
.do_unaligned_access = mips_cpu_do_unaligned_access,
.io_recompile_replay_branch = mips_io_recompile_replay_branch,
@@ -18,6 +18,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/bitops.h"
+#include "qemu/main-loop.h"
#include "qemu/plugin.h"
#include "cpu.h"
@@ -1045,6 +1046,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
int cause = -1;
uint64_t last_pc = env->active_tc.PC;
+ BQL_LOCK_GUARD();
+
if (qemu_loglevel_mask(CPU_LOG_INT)
&& cs->exception_index != EXCP_EXT_INTERRUPT) {
qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
@@ -7498,7 +7498,7 @@ static const TCGCPUOps ppc_tcg_ops = {
.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
.cpu_exec_halt = ppc_cpu_has_work,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = ppc_cpu_do_interrupt,
+ .do_interrupt = ppc_cpu_do_interrupt,
.cpu_exec_enter = ppc_cpu_exec_enter,
.cpu_exec_exit = ppc_cpu_exec_exit,
.do_unaligned_access = ppc_cpu_do_unaligned_access,
@@ -1761,6 +1761,8 @@ void ppc_cpu_do_interrupt(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
+ BQL_LOCK_GUARD();
+
powerpc_excp(cpu, cs->exception_index);
}
@@ -289,7 +289,7 @@ const TCGCPUOps riscv_tcg_ops = {
.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
.cpu_exec_halt = riscv_cpu_has_work,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = riscv_cpu_do_interrupt,
+ .do_interrupt = riscv_cpu_do_interrupt,
.do_transaction_failed = riscv_cpu_do_transaction_failed,
.do_unaligned_access = riscv_cpu_do_unaligned_access,
.debug_excp_handler = riscv_cpu_debug_excp_handler,
@@ -229,7 +229,7 @@ static const TCGCPUOps rx_tcg_ops = {
.cpu_exec_interrupt = rx_cpu_exec_interrupt,
.cpu_exec_halt = rx_cpu_has_work,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = rx_cpu_do_interrupt,
+ .do_interrupt = rx_cpu_do_interrupt,
};
static void rx_cpu_class_init(ObjectClass *klass, const void *data)
@@ -18,6 +18,7 @@
#include "qemu/osdep.h"
#include "qemu/bitops.h"
+#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/log.h"
#include "accel/tcg/cpu-ldst.h"
@@ -47,6 +48,8 @@ void rx_cpu_do_interrupt(CPUState *cs)
uint32_t save_psw;
uint64_t last_pc = env->pc;
+ BQL_LOCK_GUARD();
+
env->in_sleep = 0;
if (env->psw_u) {
@@ -386,7 +386,7 @@ static const TCGCPUOps s390_tcg_ops = {
.cpu_exec_interrupt = s390_cpu_exec_interrupt,
.cpu_exec_halt = s390_cpu_has_work,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = s390_cpu_do_interrupt,
+ .do_interrupt = s390_cpu_do_interrupt,
.debug_excp_handler = s390x_cpu_debug_excp_handler,
.do_unaligned_access = s390x_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
@@ -28,6 +28,7 @@
#include "s390x-internal.h"
#include "tcg_s390x.h"
#ifndef CONFIG_USER_ONLY
+#include "qemu/main-loop.h"
#include "qemu/timer.h"
#include "system/address-spaces.h"
#include "system/memory.h"
@@ -503,6 +504,8 @@ void s390_cpu_do_interrupt(CPUState *cs)
bool stopped = false;
uint64_t last_pc = cpu->env.psw.addr;
+ BQL_LOCK_GUARD();
+
qemu_log_mask(CPU_LOG_INT, "%s: %d at psw=%" PRIx64 ":%" PRIx64 "\n",
__func__, cs->exception_index, env->psw.mask, env->psw.addr);
@@ -314,7 +314,7 @@ static const TCGCPUOps superh_tcg_ops = {
.cpu_exec_interrupt = superh_cpu_exec_interrupt,
.cpu_exec_halt = superh_cpu_has_work,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = superh_cpu_do_interrupt,
+ .do_interrupt = superh_cpu_do_interrupt,
.do_unaligned_access = superh_cpu_do_unaligned_access,
.io_recompile_replay_branch = superh_io_recompile_replay_branch,
#endif /* !CONFIG_USER_ONLY */
@@ -28,6 +28,7 @@
#include "qemu/plugin.h"
#if !defined(CONFIG_USER_ONLY)
+#include "qemu/main-loop.h"
#include "hw/sh4/sh_intc.h"
#include "system/runstate.h"
#endif
@@ -64,6 +65,8 @@ void superh_cpu_do_interrupt(CPUState *cs)
int do_exp, irq_vector = cs->exception_index;
uint64_t last_pc = env->pc;
+ BQL_LOCK_GUARD();
+
/* prioritize exceptions over interrupts */
do_exp = cs->exception_index != -1;
@@ -1076,7 +1076,7 @@ static const TCGCPUOps sparc_tcg_ops = {
.cpu_exec_interrupt = sparc_cpu_exec_interrupt,
.cpu_exec_halt = sparc_cpu_has_work,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = sparc_cpu_do_interrupt,
+ .do_interrupt = sparc_cpu_do_interrupt,
.do_transaction_failed = sparc_cpu_do_transaction_failed,
.do_unaligned_access = sparc_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
@@ -105,6 +105,8 @@ void sparc_cpu_do_interrupt(CPUState *cs)
CPUSPARCState *env = cpu_env(cs);
int cwp, intno = cs->exception_index;
+ BQL_LOCK_GUARD();
+
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
const char *name;
@@ -138,6 +138,8 @@ void sparc_cpu_do_interrupt(CPUState *cs)
int intno = cs->exception_index;
trap_state *tsptr;
+ BQL_LOCK_GUARD();
+
#ifdef DEBUG_PCALL
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
@@ -327,7 +327,7 @@ static const TCGCPUOps xtensa_tcg_ops = {
.cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
.cpu_exec_halt = xtensa_cpu_has_work,
.cpu_exec_reset = cpu_reset,
- .do_interrupt_locked = xtensa_cpu_do_interrupt,
+ .do_interrupt = xtensa_cpu_do_interrupt,
.do_transaction_failed = xtensa_cpu_do_transaction_failed,
.do_unaligned_access = xtensa_cpu_do_unaligned_access,
.debug_check_breakpoint = xtensa_debug_check_breakpoint,
@@ -208,6 +208,8 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
{
CPUXtensaState *env = cpu_env(cs);
+ BQL_LOCK_GUARD();
+
if (cs->exception_index == EXC_IRQ) {
uint64_t last_pc = env->pc;
Migrate 13 targets to acquire the BQL explicitly within their do_interrupt() implementations instead of relying on the TCG core to hold it. This allows per-target control over locking granularity and paves the way for fine-grained BQL optimization. Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> --- target/alpha/cpu.c | 2 +- target/alpha/helper.c | 3 +++ target/arm/cpu.c | 2 +- target/arm/helper.c | 1 + target/arm/tcg/cpu-v7m.c | 2 +- target/arm/tcg/m_helper.c | 2 ++ target/avr/cpu.c | 2 +- target/avr/helper.c | 3 +++ target/hppa/cpu.c | 2 +- target/hppa/int_helper.c | 2 ++ target/i386/tcg/system/seg_helper.c | 2 ++ target/i386/tcg/tcg-cpu.c | 2 +- target/mips/cpu.c | 2 +- target/mips/tcg/system/tlb_helper.c | 3 +++ target/ppc/cpu_init.c | 2 +- target/ppc/excp_helper.c | 2 ++ target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/rx/helper.c | 3 +++ target/s390x/cpu.c | 2 +- target/s390x/tcg/excp_helper.c | 3 +++ target/sh4/cpu.c | 2 +- target/sh4/helper.c | 3 +++ target/sparc/cpu.c | 2 +- target/sparc/int32_helper.c | 2 ++ target/sparc/int64_helper.c | 2 ++ target/xtensa/cpu.c | 2 +- target/xtensa/exc_helper.c | 2 ++ 28 files changed, 47 insertions(+), 14 deletions(-)