| Message ID | 20240521013029.30082-9-npiggin@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/ppc: Various TCG emulation patches | expand |
Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR > registers with simple (generic) implementations. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> > --- > target/ppc/cpu_init.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 7684a59d75..023b58a3ac 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -246,7 +246,7 @@ static void register_amr_sprs(CPUPPCState *env) > spr_register_hv(env, SPR_AMOR, "AMOR", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > + &spr_read_generic, &spr_core_lpar_write_generic, > 0); > #endif /* !CONFIG_USER_ONLY */ > } > @@ -5489,7 +5489,7 @@ static void > register_book3s_ids_sprs(CPUPPCState *env) > spr_register_hv(env, SPR_MMCRC, "MMCRC", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic32, > + &spr_read_generic, &spr_core_write_generic32, > 0x00000000); > spr_register_hv(env, SPR_MMCRH, "MMCRH", > SPR_NOACCESS, SPR_NOACCESS, > @@ -5529,7 +5529,7 @@ static void > register_book3s_ids_sprs(CPUPPCState *env) > spr_register_hv(env, SPR_HRMOR, "HRMOR", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > + &spr_read_generic, &spr_core_write_generic, > 0x00000000); > } > > @@ -5757,7 +5757,7 @@ static void > register_power_common_book4_sprs(CPUPPCState *env) > spr_register_hv(env, SPR_TSCR, "TSCR", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic32, > + &spr_read_generic, &spr_core_write_generic32, > 0x00000000); > spr_register_hv(env, SPR_HMER, "HMER", > SPR_NOACCESS, SPR_NOACCESS, > @@ -5767,7 +5767,7 @@ static void > register_power_common_book4_sprs(CPUPPCState *env) > spr_register_hv(env, SPR_HMEER, "HMEER", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > + &spr_read_generic, &spr_core_write_generic, > 0x00000000); > spr_register_hv(env, SPR_TFMR, "TFMR", > SPR_NOACCESS, SPR_NOACCESS, > @@ -5843,7 +5843,7 @@ static void > register_power8_rpr_sprs(CPUPPCState *env) > spr_register_hv(env, SPR_RPR, "RPR", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > + &spr_read_generic, &spr_core_write_generic, > 0x00000103070F1F3F); > #endif > }
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 7684a59d75..023b58a3ac 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -246,7 +246,7 @@ static void register_amr_sprs(CPUPPCState *env) spr_register_hv(env, SPR_AMOR, "AMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_core_lpar_write_generic, 0); #endif /* !CONFIG_USER_ONLY */ } @@ -5489,7 +5489,7 @@ static void register_book3s_ids_sprs(CPUPPCState *env) spr_register_hv(env, SPR_MMCRC, "MMCRC", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, + &spr_read_generic, &spr_core_write_generic32, 0x00000000); spr_register_hv(env, SPR_MMCRH, "MMCRH", SPR_NOACCESS, SPR_NOACCESS, @@ -5529,7 +5529,7 @@ static void register_book3s_ids_sprs(CPUPPCState *env) spr_register_hv(env, SPR_HRMOR, "HRMOR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_core_write_generic, 0x00000000); } @@ -5757,7 +5757,7 @@ static void register_power_common_book4_sprs(CPUPPCState *env) spr_register_hv(env, SPR_TSCR, "TSCR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, + &spr_read_generic, &spr_core_write_generic32, 0x00000000); spr_register_hv(env, SPR_HMER, "HMER", SPR_NOACCESS, SPR_NOACCESS, @@ -5767,7 +5767,7 @@ static void register_power_common_book4_sprs(CPUPPCState *env) spr_register_hv(env, SPR_HMEER, "HMEER", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_core_write_generic, 0x00000000); spr_register_hv(env, SPR_TFMR, "TFMR", SPR_NOACCESS, SPR_NOACCESS, @@ -5843,7 +5843,7 @@ static void register_power8_rpr_sprs(CPUPPCState *env) spr_register_hv(env, SPR_RPR, "RPR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_core_write_generic, 0x00000103070F1F3F); #endif }
AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR registers with simple (generic) implementations. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- target/ppc/cpu_init.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)