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[PULL,24/43] target/hppa: Use TCG_COND_TST* in trans_bb_imm

Message ID	20240515094043.82850-25-richard.henderson@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: Helge Deller <deller@gmx.de>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PULL 24/43] target/hppa: Use TCG_COND_TST* in trans_bb_imm Date: Wed, 15 May 2024 11:40:24 +0200 Message-Id: <20240515094043.82850-25-richard.henderson@linaro.org> In-Reply-To: <20240515094043.82850-1-richard.henderson@linaro.org> References: <20240515094043.82850-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/43] target/hppa: Move cpu_get_tb_cpu_state out of line \| expand [PULL,01/43] target/hppa: Move cpu_get_tb_cpu_state out of line [PULL,02/43] target/hppa: Use hppa_form_gva_psw in hppa_cpu_get_pc [PULL,03/43] target/hppa: Move constant destination check into use_goto_tb [PULL,04/43] target/hppa: Pass displacement to do_dbranch [PULL,05/43] target/hppa: Allow prior nullification in do_ibranch [PULL,06/43] target/hppa: Use CF_BP_PAGE instead of cpu_breakpoint_test [PULL,07/43] target/hppa: Add install_iaq_entries [PULL,08/43] target/hppa: Add install_link [PULL,09/43] target/hppa: Delay computation of IAQ_Next [PULL,10/43] target/hppa: Skip nullified insns in unconditional dbranch path [PULL,11/43] target/hppa: Simplify TB end [PULL,12/43] target/hppa: Add IASQ entries to DisasContext [PULL,13/43] target/hppa: Add space arguments to install_iaq_entries [PULL,14/43] target/hppa: Add space argument to do_ibranch [PULL,15/43] target/hppa: Use umax in do_ibranch_priv [PULL,16/43] target/hppa: Always make a copy in do_ibranch_priv [PULL,17/43] target/hppa: Introduce and use DisasIAQE for branch management [PULL,18/43] target/hppa: Use displacements in DisasIAQE [PULL,19/43] target/hppa: Rename cond_make_* helpers [PULL,20/43] target/hppa: Use TCG_COND_TST* in do_cond [PULL,21/43] target/hppa: Use TCG_COND_TST* in do_log_cond [PULL,22/43] target/hppa: Use TCG_COND_TST* in do_unit_zero_cond [PULL,23/43] target/hppa: Use TCG_COND_TST* in do_unit_addsub [PULL,24/43] target/hppa: Use TCG_COND_TST* in trans_bb_imm [PULL,25/43] target/hppa: Use registerfields.h for FPSR [PULL,26/43] target/hppa: Use TCG_COND_TST* in trans_ftest [PULL,27/43] target/hppa: Remove cond_free [PULL,28/43] target/hppa: Introduce DisasDelayException [PULL,29/43] target/hppa: Use delay_excp for conditional traps [PULL,30/43] target/hppa: Use delay_excp for conditional trap on overflow [PULL,31/43] linux-user/hppa: Force all code addresses to PRIV_USER [PULL,32/43] target/hppa: Store full iaoq_f and page offset of iaoq_b in TB [PULL,33/43] target/hppa: Do not mask in copy_iaoq_entry [PULL,34/43] target/hppa: Improve hppa_cpu_dump_state [PULL,35/43] target/hppa: Split PSW X and B into their own field [PULL,36/43] target/hppa: Manage PSW_X and PSW_B in translator [PULL,37/43] target/hppa: Implement PSW_B [PULL,38/43] target/hppa: Implement PSW_X [PULL,39/43] target/hppa: Drop tlb_entry return from hppa_get_physical_address [PULL,40/43] target/hppa: Adjust priv for B,GATE at runtime [PULL,41/43] target/hppa: Implement CF_PCREL [PULL,42/43] target/hppa: Log cpu state at interrupt [PULL,43/43] target/hppa: Log cpu state on return-from-interrupt

Commit Message

Richard Henderson May 15, 2024, 9:40 a.m. UTC

Reviewed-by: Helge Deller <deller@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff mbox series

Patch

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4e49bd2b67..af6be5100c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3516,18 +3516,12 @@  static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a)
 
 static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a)
 {
-    TCGv_i64 tmp, tcg_r;
     DisasCond cond;
-    int p;
+    int p = a->p | (a->d ? 0 : 32);
 
     nullify_over(ctx);
-
-    tmp = tcg_temp_new_i64();
-    tcg_r = load_gpr(ctx, a->r);
-    p = a->p | (a->d ? 0 : 32);
-    tcg_gen_shli_i64(tmp, tcg_r, p);
-
-    cond = cond_make_ti(a->c ? TCG_COND_GE : TCG_COND_LT, tmp, 0);
+    cond = cond_make_vi(a->c ? TCG_COND_TSTEQ : TCG_COND_TSTNE,
+                        load_gpr(ctx, a->r), 1ull << (63 - p));
     return do_cbranch(ctx, a->disp, a->n, &cond);
 }