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Fri, 03 May 2024 00:21:01 -0700 (PDT) Received: from m1x-phil.lan ([176.176.179.187]) by smtp.gmail.com with ESMTPSA id b20-20020a05600c4e1400b0041892857924sm4635480wmq.36.2024.05.03.00.21.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 03 May 2024 00:21:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 8/9] target/alpha: Split out gen_pc_disp Date: Fri, 3 May 2024 09:20:12 +0200 Message-ID: <20240503072014.24751-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240503072014.24751-1-philmd@linaro.org> References: <20240503072014.24751-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Richard Henderson Prepare for pcrel by not modifying cpu_pc before use, in the case of JSR. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/translate.c | 41 ++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index c1a55e5153..86402d96d5 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -252,6 +252,11 @@ static void st_flag_byte(TCGv val, unsigned shift) tcg_gen_st8_i64(val, tcg_env, get_flag_ofs(shift)); } +static void gen_pc_disp(DisasContext *ctx, TCGv dest, int32_t disp) +{ + tcg_gen_movi_i64(dest, ctx->base.pc_next + disp); +} + static void gen_excp_1(int exception, int error_code) { TCGv_i32 tmp1, tmp2; @@ -263,7 +268,7 @@ static void gen_excp_1(int exception, int error_code) static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code) { - tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + gen_pc_disp(ctx, cpu_pc, 0); gen_excp_1(exception, error_code); return DISAS_NORETURN; } @@ -427,14 +432,12 @@ static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb, static void gen_goto_tb(DisasContext *ctx, int idx, int32_t disp) { - uint64_t dest = ctx->base.pc_next + disp; - - if (translator_use_goto_tb(&ctx->base, dest)) { + if (translator_use_goto_tb(&ctx->base, ctx->base.pc_next + disp)) { tcg_gen_goto_tb(idx); - tcg_gen_movi_i64(cpu_pc, dest); + gen_pc_disp(ctx, cpu_pc, disp); tcg_gen_exit_tb(ctx->base.tb, idx); } else { - tcg_gen_movi_i64(cpu_pc, dest); + gen_pc_disp(ctx, cpu_pc, disp); tcg_gen_lookup_and_goto_ptr(); } } @@ -442,7 +445,7 @@ static void gen_goto_tb(DisasContext *ctx, int idx, int32_t disp) static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp) { if (ra != 31) { - tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next); + gen_pc_disp(ctx, ctx->ir[ra], 0); } /* Notice branch-to-next; used to initialize RA with the PC. */ @@ -1091,7 +1094,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) } /* Allow interrupts to be recognized right away. */ - tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + gen_pc_disp(ctx, cpu_pc, 0); return DISAS_PC_UPDATED_NOCHAIN; case 0x36: @@ -1138,19 +1141,17 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) #else { TCGv tmp = tcg_temp_new(); - uint64_t exc_addr = ctx->base.pc_next; - uint64_t entry = ctx->palbr; + uint64_t entry; + gen_pc_disp(ctx, tmp, 0); if (ctx->tbflags & ENV_FLAG_PAL_MODE) { - exc_addr |= 1; + tcg_gen_ori_i64(tmp, tmp, 1); } else { - tcg_gen_movi_i64(tmp, 1); - st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT); + st_flag_byte(tcg_constant_i64(1), ENV_FLAG_PAL_SHIFT); } - - tcg_gen_movi_i64(tmp, exc_addr); tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr)); + entry = ctx->palbr; entry += (palcode & 0x80 ? 0x2000 + (palcode - 0x80) * 64 : 0x1000 + palcode * 64); @@ -2344,9 +2345,13 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) /* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch prediction stack action, which of course we don't implement. */ vb = load_gpr(ctx, rb); - tcg_gen_andi_i64(cpu_pc, vb, ~3); if (ra != 31) { - tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next); + tmp = tcg_temp_new(); + tcg_gen_andi_i64(tmp, vb, ~3); + gen_pc_disp(ctx, ctx->ir[ra], 0); + tcg_gen_mov_i64(cpu_pc, tmp); + } else { + tcg_gen_andi_i64(cpu_pc, vb, ~3); } ret = DISAS_PC_UPDATED; break; @@ -2908,7 +2913,7 @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_goto_tb(ctx, 0, 0); break; case DISAS_PC_STALE: - tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + gen_pc_disp(ctx, cpu_pc, 0); /* FALLTHRU */ case DISAS_PC_UPDATED: tcg_gen_lookup_and_goto_ptr();