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Fri, 03 May 2024 00:20:22 -0700 (PDT) Received: from m1x-phil.lan ([176.176.179.187]) by smtp.gmail.com with ESMTPSA id s7-20020a05600c384700b0041c12324eb6sm8377191wmr.22.2024.05.03.00.20.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 03 May 2024 00:20:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH v2 1/9] target/alpha: Use cpu_env in preference to ALPHA_CPU Date: Fri, 3 May 2024 09:20:05 +0200 Message-ID: <20240503072014.24751-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240503072014.24751-1-philmd@linaro.org> References: <20240503072014.24751-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Richard Henderson ALPHA_CPU has a dynamic object type assert, which is unnecessary considering that these are all class hooks. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.c | 15 ++++++--------- target/alpha/helper.c | 8 ++++---- 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 05f9ee41e9..f98d022671 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -28,25 +28,22 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { - AlphaCPU *cpu = ALPHA_CPU(cs); - - cpu->env.pc = value; + CPUAlphaState *env = cpu_env(cs); + env->pc = value; } static vaddr alpha_cpu_get_pc(CPUState *cs) { - AlphaCPU *cpu = ALPHA_CPU(cs); - - return cpu->env.pc; + CPUAlphaState *env = cpu_env(cs); + return env->pc; } static void alpha_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - AlphaCPU *cpu = ALPHA_CPU(cs); - - cpu->env.pc = data[0]; + CPUAlphaState *env = cpu_env(cs); + env->pc = data[0]; } static bool alpha_cpu_has_work(CPUState *cs) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index d6d4353edd..c5e4958f8b 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -124,7 +124,7 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, MMUAccessType access_type, bool maperr, uintptr_t retaddr) { - AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = cpu_env(cs); target_ulong mmcsr, cause; /* Assuming !maperr, infer the missing protection. */ @@ -155,9 +155,9 @@ void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address, } /* Record the arguments that PALcode would give to the kernel. */ - cpu->env.trap_arg0 = address; - cpu->env.trap_arg1 = mmcsr; - cpu->env.trap_arg2 = cause; + env->trap_arg0 = address; + env->trap_arg1 = mmcsr; + env->trap_arg2 = cause; } #else /* Returns the OSF/1 entMM failure indication, or -1 on success. */