diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a6abb48b55..8b8dd62761 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1846,3 +1846,25 @@ DEF_HELPER_6(th_vnmsub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(th_vnmsub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(th_vnmsub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(th_vnmsub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(th_vwmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index d84edd90ca..bfa3a26f78 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -1567,19 +1567,21 @@ GEN_OPIVX_TRANS_TH(th_vnmsac_vx, opivx_check_th)
 GEN_OPIVX_TRANS_TH(th_vmadd_vx, opivx_check_th)
 GEN_OPIVX_TRANS_TH(th_vnmsub_vx, opivx_check_th)
 
+/* Vector Widening Integer Multiply-Add Instructions */
+GEN_OPIVV_WIDEN_TRANS_TH(th_vwmaccu_vv, opivx_widen_check_th)
+GEN_OPIVV_WIDEN_TRANS_TH(th_vwmacc_vv, opivx_widen_check_th)
+GEN_OPIVV_WIDEN_TRANS_TH(th_vwmaccsu_vv, opivx_widen_check_th)
+GEN_OPIVX_WIDEN_TRANS_TH(th_vwmaccu_vx, opivx_widen_check_th)
+GEN_OPIVX_WIDEN_TRANS_TH(th_vwmacc_vx, opivx_widen_check_th)
+GEN_OPIVX_WIDEN_TRANS_TH(th_vwmaccsu_vx, opivx_widen_check_th)
+GEN_OPIVX_WIDEN_TRANS_TH(th_vwmaccus_vx, opivx_widen_check_th)
+
 #define TH_TRANS_STUB(NAME)                                \
 static bool trans_##NAME(DisasContext *s, arg_##NAME *a)   \
 {                                                          \
     return require_xtheadvector(s);                        \
 }
 
-TH_TRANS_STUB(th_vwmaccu_vv)
-TH_TRANS_STUB(th_vwmaccu_vx)
-TH_TRANS_STUB(th_vwmacc_vv)
-TH_TRANS_STUB(th_vwmacc_vx)
-TH_TRANS_STUB(th_vwmaccsu_vv)
-TH_TRANS_STUB(th_vwmaccsu_vx)
-TH_TRANS_STUB(th_vwmaccus_vx)
 TH_TRANS_STUB(th_vmv_v_v)
 TH_TRANS_STUB(th_vmv_v_x)
 TH_TRANS_STUB(th_vmv_v_i)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index b312d67f87..06ca77691d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -647,9 +647,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
  */
 
 /* (TD, T1, T2, TX1, TX2) */
-#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
-#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
-#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
 #define NOP_SSS_B int8_t, int8_t, int16_t, int8_t, int16_t
 #define NOP_SSS_H int16_t, int16_t, int32_t, int16_t, int32_t
 #define NOP_SSS_W int32_t, int32_t, int64_t, int32_t, int64_t
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index c3d9752e2e..e99caa8e2d 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -252,6 +252,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,    \
 #define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t
 #define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t
 #define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t
+#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t
+#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t
+#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t
 
 /* share functions */
 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c
index ccf6eb8a43..19aad626c9 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -1878,3 +1878,48 @@ GEN_TH_VX(th_vnmsub_vx_b, 1, 1, clearb_th)
 GEN_TH_VX(th_vnmsub_vx_h, 2, 2, clearh_th)
 GEN_TH_VX(th_vnmsub_vx_w, 4, 4, clearl_th)
 GEN_TH_VX(th_vnmsub_vx_d, 8, 8, clearq_th)
+
+/* Vector Widening Integer Multiply-Add Instructions */
+THCALL(TH_OPIVV3, th_vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, TH_MACC)
+THCALL(TH_OPIVV3, th_vwmaccu_vv_h, WOP_UUU_H, H4, H2, H2, TH_MACC)
+THCALL(TH_OPIVV3, th_vwmaccu_vv_w, WOP_UUU_W, H8, H4, H4, TH_MACC)
+THCALL(TH_OPIVV3, th_vwmacc_vv_b, WOP_SSS_B, H2, H1, H1, TH_MACC)
+THCALL(TH_OPIVV3, th_vwmacc_vv_h, WOP_SSS_H, H4, H2, H2, TH_MACC)
+THCALL(TH_OPIVV3, th_vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, TH_MACC)
+THCALL(TH_OPIVV3, th_vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, TH_MACC)
+THCALL(TH_OPIVV3, th_vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, TH_MACC)
+THCALL(TH_OPIVV3, th_vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, TH_MACC)
+GEN_TH_VV(th_vwmaccu_vv_b, 1, 2, clearh_th)
+GEN_TH_VV(th_vwmaccu_vv_h, 2, 4, clearl_th)
+GEN_TH_VV(th_vwmaccu_vv_w, 4, 8, clearq_th)
+GEN_TH_VV(th_vwmacc_vv_b, 1, 2, clearh_th)
+GEN_TH_VV(th_vwmacc_vv_h, 2, 4, clearl_th)
+GEN_TH_VV(th_vwmacc_vv_w, 4, 8, clearq_th)
+GEN_TH_VV(th_vwmaccsu_vv_b, 1, 2, clearh_th)
+GEN_TH_VV(th_vwmaccsu_vv_h, 2, 4, clearl_th)
+GEN_TH_VV(th_vwmaccsu_vv_w, 4, 8, clearq_th)
+
+THCALL(TH_OPIVX3, th_vwmaccu_vx_b, WOP_UUU_B, H2, H1, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmaccu_vx_h, WOP_UUU_H, H4, H2, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmaccu_vx_w, WOP_UUU_W, H8, H4, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmacc_vx_b, WOP_SSS_B, H2, H1, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmacc_vx_h, WOP_SSS_H, H4, H2, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmacc_vx_w, WOP_SSS_W, H8, H4, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmaccsu_vx_b, WOP_SSU_B, H2, H1, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmaccsu_vx_h, WOP_SSU_H, H4, H2, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmaccsu_vx_w, WOP_SSU_W, H8, H4, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmaccus_vx_b, WOP_SUS_B, H2, H1, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmaccus_vx_h, WOP_SUS_H, H4, H2, TH_MACC)
+THCALL(TH_OPIVX3, th_vwmaccus_vx_w, WOP_SUS_W, H8, H4, TH_MACC)
+GEN_TH_VX(th_vwmaccu_vx_b, 1, 2, clearh_th)
+GEN_TH_VX(th_vwmaccu_vx_h, 2, 4, clearl_th)
+GEN_TH_VX(th_vwmaccu_vx_w, 4, 8, clearq_th)
+GEN_TH_VX(th_vwmacc_vx_b, 1, 2, clearh_th)
+GEN_TH_VX(th_vwmacc_vx_h, 2, 4, clearl_th)
+GEN_TH_VX(th_vwmacc_vx_w, 4, 8, clearq_th)
+GEN_TH_VX(th_vwmaccsu_vx_b, 1, 2, clearh_th)
+GEN_TH_VX(th_vwmaccsu_vx_h, 2, 4, clearl_th)
+GEN_TH_VX(th_vwmaccsu_vx_w, 4, 8, clearq_th)
+GEN_TH_VX(th_vwmaccus_vx_b, 1, 2, clearh_th)
+GEN_TH_VX(th_vwmaccus_vx_h, 2, 4, clearl_th)
+GEN_TH_VX(th_vwmaccus_vx_w, 4, 8, clearq_th)
