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envelope-from=3l_oTZggKChQC68CDuzu08805y.w86Ay6E-xyFy578707E.8B0@flex--smostafa.bounces.google.com; helo=mail-wr1-x44a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add property that sets the OAS of the SMMU, this in not used in this patch. Signed-off-by: Mostafa Saleh --- hw/arm/smmuv3-internal.h | 3 ++- hw/arm/smmuv3.c | 29 ++++++++++++++++++++++++++++- include/hw/arm/smmuv3.h | 1 + 3 files changed, 31 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index b0d7ad6da3..41612bb9ff 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -105,7 +105,8 @@ REG32(IDR5, 0x14) FIELD(IDR5, VAX, 10, 2); FIELD(IDR5, STALL_MAX, 16, 16); -#define SMMU_IDR5_OAS 4 +#define SMMU_IDR5_OAS_DEF 4 /* 44 bits. */ +#define SMMU_IDR5_OAS_MAX 5 /* 48 bits. */ REG32(IIDR, 0x18) REG32(AIDR, 0x1c) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c377c05379..a9e35c41b7 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -299,7 +299,9 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2); - s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44 bits */ + /* PTW doesn't support 52 bits. */ + s->oas = MIN(s->oas, SMMU_IDR5_OAS_MAX); + s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, s->oas); /* 4K, 16K and 64K granule support */ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); @@ -1878,11 +1880,34 @@ static const VMStateDescription vmstate_gbpa = { } }; +static const VMStateDescription vmstate_oas = { + .name = "smmuv3/oas", + .version_id = 1, + .minimum_version_id = 1, + .fields = (const VMStateField[]) { + VMSTATE_INT32(oas, SMMUv3State), + VMSTATE_END_OF_LIST() + } +}; + +static int smmuv3_preload(void *opaque) +{ + SMMUv3State *s = opaque; + + /* + * In case it wasn't migrated, use the value used + * by older QEMU. + */ + s->oas = SMMU_IDR5_OAS_DEF; + return 0; +} + static const VMStateDescription vmstate_smmuv3 = { .name = "smmuv3", .version_id = 1, .minimum_version_id = 1, .priority = MIG_PRI_IOMMU, + .pre_load = smmuv3_preload, .fields = (const VMStateField[]) { VMSTATE_UINT32(features, SMMUv3State), VMSTATE_UINT8(sid_size, SMMUv3State), @@ -1910,6 +1935,7 @@ static const VMStateDescription vmstate_smmuv3 = { }, .subsections = (const VMStateDescription * const []) { &vmstate_gbpa, + &vmstate_oas, NULL } }; @@ -1922,6 +1948,7 @@ static Property smmuv3_properties[] = { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + DEFINE_PROP_INT32("oas", SMMUv3State, oas, SMMU_IDR5_OAS_DEF), DEFINE_PROP_END_OF_LIST() }; diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d183a62766..00a9eb4467 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -63,6 +63,7 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; char *stage; + int32_t oas; }; typedef enum {