diff mbox series

[08/13] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits

Message ID 20240311185200.2185753-9-npiggin@gmail.com
State New
Headers show
Series misc ppc patches | expand

Commit Message

Nicholas Piggin March 11, 2024, 6:51 p.m. UTC 
Copy the pa-features arrays from spapr, adjusting slightly as
described in comments.

Cc: "Cédric Le Goater" <clg@kaod.org>
Cc: "Frédéric Barrat" <fbarrat@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/ppc/pnv.c   | 67 ++++++++++++++++++++++++++++++++++++++++++++++++--
 hw/ppc/spapr.c |  1 +
 2 files changed, 66 insertions(+), 2 deletions(-)

Comments

Cédric Le Goater March 12, 2024, 8:06 a.m. UTC | #1 
On 3/11/24 19:51, Nicholas Piggin wrote:
> Copy the pa-features arrays from spapr, adjusting slightly as
> described in comments.
> 
> Cc: "Cédric Le Goater" <clg@kaod.org>
> Cc: "Frédéric Barrat" <fbarrat@linux.ibm.com>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>   hw/ppc/pnv.c   | 67 ++++++++++++++++++++++++++++++++++++++++++++++++--
>   hw/ppc/spapr.c |  1 +
>   2 files changed, 66 insertions(+), 2 deletions(-)
> 
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 52d964f77a..3e30c08420 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -332,6 +332,35 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
>       }
>   }
>   
> +/*
> + * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
> + */
> +static const uint8_t pa_features_300[] = { 66, 0,
> +    /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
> +    /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
> +    0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
> +    /* 6: DS207 */
> +    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
> +    /* 16: Vector */
> +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> +    /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
> +    /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
> +    /* 32: LE atomic, 34: EBB + ext EBB */
> +    0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
> +    /* 40: Radix MMU */
> +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
> +    /* 42: PM, 44: PC RA, 46: SC vec'd */
> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
> +    /* 48: SIMD, 50: QP BFP, 52: String */
> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
> +    /* 54: DecFP, 56: DecI, 58: SHA */
> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
> +    /* 60: NM atomic, 62: RNG */
> +    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
> +};
> +
>   static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
>   {
>       static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
> @@ -349,7 +378,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
>           offset = pnv_dt_core(chip, pnv_core, fdt);
>   
>           _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
> -                           pa_features_207, sizeof(pa_features_207))));
> +                           pa_features_300, sizeof(pa_features_300))));
>       }
>   
>       if (chip->ram_size) {
> @@ -359,6 +388,40 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
>       pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
>   }
>   
> +/*
> + * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
> + * always disables copy/paste.
> + */
> +static const uint8_t pa_features_31[] = { 74, 0,
> +    /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
> +    /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
> +    0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
> +    /* 6: DS207 */
> +    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
> +    /* 16: Vector */
> +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> +    /* 18: Vec. Scalar, 20: Vec. XOR */
> +    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
> +    /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
> +    /* 32: LE atomic, 34: EBB + ext EBB */
> +    0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
> +    /* 40: Radix MMU */
> +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
> +    /* 42: PM, 44: PC RA, 46: SC vec'd */
> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
> +    /* 48: SIMD, 50: QP BFP, 52: String */
> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
> +    /* 54: DecFP, 56: DecI, 58: SHA */
> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
> +    /* 60: NM atomic, 62: RNG */
> +    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
> +    /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
> +    0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
> +    /* 72: [P]HASHCHK */
> +    0x80, 0x00,                         /* 72 - 73 */
> +};
> +
>   static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
>   {
>       static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
> @@ -376,7 +439,7 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
>           offset = pnv_dt_core(chip, pnv_core, fdt);
>   
>           _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
> -                           pa_features_207, sizeof(pa_features_207))));
> +                           pa_features_31, sizeof(pa_features_31))));
>       }
>   
>       if (chip->ram_size) {
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 128bfe11a8..b53c13e037 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -233,6 +233,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
>                                    PowerPCCPU *cpu,
>                                    void *fdt, int offset)
>   {
> +    /* These should be kept in sync with pnv */

yes. In that case, the array definition should be moved under target/ppc/.
May be under PowerPCCPUClass ?

Thanks,

C.

>       uint8_t pa_features_206[] = { 6, 0,
>           0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 };
>       uint8_t pa_features_207[] = { 24, 0,
Nicholas Piggin March 12, 2024, 8:54 a.m. UTC | #2 
On Tue Mar 12, 2024 at 6:06 PM AEST, Cédric Le Goater wrote:
> On 3/11/24 19:51, Nicholas Piggin wrote:
> > Copy the pa-features arrays from spapr, adjusting slightly as
> > described in comments.
> > 
> > Cc: "Cédric Le Goater" <clg@kaod.org>
> > Cc: "Frédéric Barrat" <fbarrat@linux.ibm.com>
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> > ---
> >   hw/ppc/pnv.c   | 67 ++++++++++++++++++++++++++++++++++++++++++++++++--
> >   hw/ppc/spapr.c |  1 +
> >   2 files changed, 66 insertions(+), 2 deletions(-)
> > 
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index 52d964f77a..3e30c08420 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -332,6 +332,35 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
> >       }
> >   }
> >   
> > +/*
> > + * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
> > + */
> > +static const uint8_t pa_features_300[] = { 66, 0,
> > +    /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
> > +    /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
> > +    0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
> > +    /* 6: DS207 */
> > +    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
> > +    /* 16: Vector */
> > +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> > +    /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
> > +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
> > +    /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
> > +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
> > +    /* 32: LE atomic, 34: EBB + ext EBB */
> > +    0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
> > +    /* 40: Radix MMU */
> > +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
> > +    /* 42: PM, 44: PC RA, 46: SC vec'd */
> > +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
> > +    /* 48: SIMD, 50: QP BFP, 52: String */
> > +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
> > +    /* 54: DecFP, 56: DecI, 58: SHA */
> > +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
> > +    /* 60: NM atomic, 62: RNG */
> > +    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
> > +};
> > +
> >   static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
> >   {
> >       static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
> > @@ -349,7 +378,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
> >           offset = pnv_dt_core(chip, pnv_core, fdt);
> >   
> >           _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
> > -                           pa_features_207, sizeof(pa_features_207))));
> > +                           pa_features_300, sizeof(pa_features_300))));
> >       }
> >   
> >       if (chip->ram_size) {
> > @@ -359,6 +388,40 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
> >       pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
> >   }
> >   
> > +/*
> > + * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
> > + * always disables copy/paste.
> > + */
> > +static const uint8_t pa_features_31[] = { 74, 0,
> > +    /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
> > +    /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
> > +    0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
> > +    /* 6: DS207 */
> > +    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
> > +    /* 16: Vector */
> > +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> > +    /* 18: Vec. Scalar, 20: Vec. XOR */
> > +    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
> > +    /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
> > +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
> > +    /* 32: LE atomic, 34: EBB + ext EBB */
> > +    0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
> > +    /* 40: Radix MMU */
> > +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
> > +    /* 42: PM, 44: PC RA, 46: SC vec'd */
> > +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
> > +    /* 48: SIMD, 50: QP BFP, 52: String */
> > +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
> > +    /* 54: DecFP, 56: DecI, 58: SHA */
> > +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
> > +    /* 60: NM atomic, 62: RNG */
> > +    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
> > +    /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
> > +    0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
> > +    /* 72: [P]HASHCHK */
> > +    0x80, 0x00,                         /* 72 - 73 */
> > +};
> > +
> >   static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
> >   {
> >       static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
> > @@ -376,7 +439,7 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
> >           offset = pnv_dt_core(chip, pnv_core, fdt);
> >   
> >           _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
> > -                           pa_features_207, sizeof(pa_features_207))));
> > +                           pa_features_31, sizeof(pa_features_31))));
> >       }
> >   
> >       if (chip->ram_size) {
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index 128bfe11a8..b53c13e037 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -233,6 +233,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
> >                                    PowerPCCPU *cpu,
> >                                    void *fdt, int offset)
> >   {
> > +    /* These should be kept in sync with pnv */
>
> yes. In that case, the array definition should be moved under target/ppc/.
> May be under PowerPCCPUClass ?

Yeah PowerPCCPUClass might be a good idea, although I'm not quite
decided whether it's best to just store the arrays there, or make a
list of features in another format and have a builder function to
turn that into the dt array. There's also a few differences between
spapr and pnv that I haven't worked out a nice way to handle yet.
I have a pi-features property to add too which is similar.

So yes this is a bit ugly but we're already duplicating and open coding
arrays so I'd like to just get this in to fix the missing P10 bits,
and refactor it afterwards.

Thanks,
Nick
Cédric Le Goater March 12, 2024, 9:14 a.m. UTC | #3 
On 3/12/24 09:54, Nicholas Piggin wrote:
> On Tue Mar 12, 2024 at 6:06 PM AEST, Cédric Le Goater wrote:
>> On 3/11/24 19:51, Nicholas Piggin wrote:
>>> Copy the pa-features arrays from spapr, adjusting slightly as
>>> described in comments.
>>>
>>> Cc: "Cédric Le Goater" <clg@kaod.org>
>>> Cc: "Frédéric Barrat" <fbarrat@linux.ibm.com>
>>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>>> ---
>>>    hw/ppc/pnv.c   | 67 ++++++++++++++++++++++++++++++++++++++++++++++++--
>>>    hw/ppc/spapr.c |  1 +
>>>    2 files changed, 66 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>>> index 52d964f77a..3e30c08420 100644
>>> --- a/hw/ppc/pnv.c
>>> +++ b/hw/ppc/pnv.c
>>> @@ -332,6 +332,35 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
>>>        }
>>>    }
>>>    
>>> +/*
>>> + * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
>>> + */
>>> +static const uint8_t pa_features_300[] = { 66, 0,
>>> +    /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
>>> +    /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
>>> +    0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
>>> +    /* 6: DS207 */
>>> +    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
>>> +    /* 16: Vector */
>>> +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
>>> +    /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
>>> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
>>> +    /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
>>> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
>>> +    /* 32: LE atomic, 34: EBB + ext EBB */
>>> +    0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
>>> +    /* 40: Radix MMU */
>>> +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
>>> +    /* 42: PM, 44: PC RA, 46: SC vec'd */
>>> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
>>> +    /* 48: SIMD, 50: QP BFP, 52: String */
>>> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
>>> +    /* 54: DecFP, 56: DecI, 58: SHA */
>>> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
>>> +    /* 60: NM atomic, 62: RNG */
>>> +    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
>>> +};
>>> +
>>>    static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
>>>    {
>>>        static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
>>> @@ -349,7 +378,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
>>>            offset = pnv_dt_core(chip, pnv_core, fdt);
>>>    
>>>            _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
>>> -                           pa_features_207, sizeof(pa_features_207))));
>>> +                           pa_features_300, sizeof(pa_features_300))));
>>>        }
>>>    
>>>        if (chip->ram_size) {
>>> @@ -359,6 +388,40 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
>>>        pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
>>>    }
>>>    
>>> +/*
>>> + * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
>>> + * always disables copy/paste.
>>> + */
>>> +static const uint8_t pa_features_31[] = { 74, 0,
>>> +    /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
>>> +    /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
>>> +    0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
>>> +    /* 6: DS207 */
>>> +    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
>>> +    /* 16: Vector */
>>> +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
>>> +    /* 18: Vec. Scalar, 20: Vec. XOR */
>>> +    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
>>> +    /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
>>> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
>>> +    /* 32: LE atomic, 34: EBB + ext EBB */
>>> +    0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
>>> +    /* 40: Radix MMU */
>>> +    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
>>> +    /* 42: PM, 44: PC RA, 46: SC vec'd */
>>> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
>>> +    /* 48: SIMD, 50: QP BFP, 52: String */
>>> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
>>> +    /* 54: DecFP, 56: DecI, 58: SHA */
>>> +    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
>>> +    /* 60: NM atomic, 62: RNG */
>>> +    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
>>> +    /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
>>> +    0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
>>> +    /* 72: [P]HASHCHK */
>>> +    0x80, 0x00,                         /* 72 - 73 */
>>> +};
>>> +
>>>    static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
>>>    {
>>>        static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
>>> @@ -376,7 +439,7 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
>>>            offset = pnv_dt_core(chip, pnv_core, fdt);
>>>    
>>>            _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
>>> -                           pa_features_207, sizeof(pa_features_207))));
>>> +                           pa_features_31, sizeof(pa_features_31))));
>>>        }
>>>    
>>>        if (chip->ram_size) {
>>> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
>>> index 128bfe11a8..b53c13e037 100644
>>> --- a/hw/ppc/spapr.c
>>> +++ b/hw/ppc/spapr.c
>>> @@ -233,6 +233,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
>>>                                     PowerPCCPU *cpu,
>>>                                     void *fdt, int offset)
>>>    {
>>> +    /* These should be kept in sync with pnv */
>>
>> yes. In that case, the array definition should be moved under target/ppc/.
>> May be under PowerPCCPUClass ?
> 
> Yeah PowerPCCPUClass might be a good idea, although I'm not quite
> decided whether it's best to just store the arrays there, or make a
> list of features in another format and have a builder function to
> turn that into the dt array. 

That would be very nice to have. The pa_features array is cryptic and
error prone.

> There's also a few differences between
> spapr and pnv that I haven't worked out a nice way to handle yet.
> I have a pi-features property to add too which is similar.
> 
> So yes this is a bit ugly but we're already duplicating and open coding
> arrays so I'd like to just get this in to fix the missing P10 bits,
> and refactor it afterwards.

OK.

Thanks,

C.
diff mbox series

Patch

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 52d964f77a..3e30c08420 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -332,6 +332,35 @@  static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
     }
 }
 
+/*
+ * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
+ */
+static const uint8_t pa_features_300[] = { 66, 0,
+    /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
+    /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+    0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
+    /* 6: DS207 */
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+    /* 16: Vector */
+    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+    /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
+    /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
+    /* 32: LE atomic, 34: EBB + ext EBB */
+    0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+    /* 40: Radix MMU */
+    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+    /* 42: PM, 44: PC RA, 46: SC vec'd */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
+    /* 48: SIMD, 50: QP BFP, 52: String */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
+    /* 54: DecFP, 56: DecI, 58: SHA */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
+    /* 60: NM atomic, 62: RNG */
+    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
+};
+
 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
 {
     static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
@@ -349,7 +378,7 @@  static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
         offset = pnv_dt_core(chip, pnv_core, fdt);
 
         _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
-                           pa_features_207, sizeof(pa_features_207))));
+                           pa_features_300, sizeof(pa_features_300))));
     }
 
     if (chip->ram_size) {
@@ -359,6 +388,40 @@  static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
     pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
 }
 
+/*
+ * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
+ * always disables copy/paste.
+ */
+static const uint8_t pa_features_31[] = { 74, 0,
+    /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
+    /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
+    0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
+    /* 6: DS207 */
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
+    /* 16: Vector */
+    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+    /* 18: Vec. Scalar, 20: Vec. XOR */
+    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
+    /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
+    /* 32: LE atomic, 34: EBB + ext EBB */
+    0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
+    /* 40: Radix MMU */
+    0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
+    /* 42: PM, 44: PC RA, 46: SC vec'd */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
+    /* 48: SIMD, 50: QP BFP, 52: String */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
+    /* 54: DecFP, 56: DecI, 58: SHA */
+    0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
+    /* 60: NM atomic, 62: RNG */
+    0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
+    /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
+    0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
+    /* 72: [P]HASHCHK */
+    0x80, 0x00,                         /* 72 - 73 */
+};
+
 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
 {
     static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
@@ -376,7 +439,7 @@  static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
         offset = pnv_dt_core(chip, pnv_core, fdt);
 
         _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
-                           pa_features_207, sizeof(pa_features_207))));
+                           pa_features_31, sizeof(pa_features_31))));
     }
 
     if (chip->ram_size) {
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 128bfe11a8..b53c13e037 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -233,6 +233,7 @@  static void spapr_dt_pa_features(SpaprMachineState *spapr,
                                  PowerPCCPU *cpu,
                                  void *fdt, int offset)
 {
+    /* These should be kept in sync with pnv */
     uint8_t pa_features_206[] = { 6, 0,
         0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 };
     uint8_t pa_features_207[] = { 24, 0,