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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.504, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org itc_reconfigure() is referenced from TCG, compile out the helpers that reference env->itu if CONFIG_MIPS_ITU is not defined. This makes it possible to build a QEMU binary that only includes boards without a CPS device (only Malta and Boston create one). Signed-off-by: Paolo Bonzini --- target/mips/tcg/translate.h | 1 + target/mips/tcg/sysemu_helper.h.inc | 19 +++++++++++++------ target/mips/tcg/sysemu/cp0_helper.c | 8 ++++++++ target/mips/tcg/translate.c | 10 ++++++++++ 4 files changed, 32 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 93a78b81212..d5458f8690d 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -9,6 +9,7 @@ #define TARGET_MIPS_TRANSLATE_H #include "cpu.h" + #include "tcg/tcg-op.h" #include "exec/translator.h" #include "exec/helper-gen.h" diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_helper.h.inc index f163af1eac7..92d01c49bf6 100644 --- a/target/mips/tcg/sysemu_helper.h.inc +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -9,6 +9,8 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ +#include CONFIG_DEVICES + /* CP0 helpers */ DEF_HELPER_1(mfc0_mvpcontrol, tl, env) DEF_HELPER_1(mfc0_mvpconf0, tl, env) @@ -31,8 +33,6 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env) DEF_HELPER_1(mfc0_tcschefback, tl, env) DEF_HELPER_1(mftc0_tcschefback, tl, env) DEF_HELPER_1(mfc0_count, tl, env) -DEF_HELPER_1(mfc0_saar, tl, env) -DEF_HELPER_1(mfhc0_saar, tl, env) DEF_HELPER_1(mftc0_entryhi, tl, env) DEF_HELPER_1(mftc0_status, tl, env) DEF_HELPER_1(mftc0_cause, tl, env) @@ -57,7 +57,6 @@ DEF_HELPER_1(dmfc0_lladdr, tl, env) DEF_HELPER_1(dmfc0_maar, tl, env) DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) -DEF_HELPER_1(dmfc0_saar, tl, env) #endif /* TARGET_MIPS64 */ DEF_HELPER_2(mtc0_index, void, env, tl) @@ -103,9 +102,6 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl) DEF_HELPER_2(mtc0_hwrena, void, env, tl) DEF_HELPER_2(mtc0_pwctl, void, env, tl) DEF_HELPER_2(mtc0_count, void, env, tl) -DEF_HELPER_2(mtc0_saari, void, env, tl) -DEF_HELPER_2(mtc0_saar, void, env, tl) -DEF_HELPER_2(mthc0_saar, void, env, tl) DEF_HELPER_2(mtc0_entryhi, void, env, tl) DEF_HELPER_2(mttc0_entryhi, void, env, tl) DEF_HELPER_2(mtc0_compare, void, env, tl) @@ -189,3 +185,14 @@ DEF_HELPER_2(lcsr_drdcsr, i64, env, tl) DEF_HELPER_3(lcsr_wrcsr, void, env, tl, tl) DEF_HELPER_3(lcsr_dwrcsr, void, env, tl, tl) #endif + +#ifdef CONFIG_MIPS_ITU +DEF_HELPER_1(mfc0_saar, tl, env) +DEF_HELPER_1(mfhc0_saar, tl, env) +DEF_HELPER_2(mtc0_saari, void, env, tl) +DEF_HELPER_2(mtc0_saar, void, env, tl) +DEF_HELPER_2(mthc0_saar, void, env, tl) +#ifdef TARGET_MIPS64 +DEF_HELPER_1(dmfc0_saar, tl, env) +#endif +#endif diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c index 62f6fb4bf65..dde890adf3f 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -21,6 +21,8 @@ */ #include "qemu/osdep.h" +#include CONFIG_DEVICES + #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" @@ -371,6 +373,7 @@ target_ulong helper_mfc0_count(CPUMIPSState *env) return (int32_t)cpu_mips_get_count(env); } +#ifdef CONFIG_MIPS_ITU target_ulong helper_mfc0_saar(CPUMIPSState *env) { if ((env->CP0_SAARI & 0x3f) < 2) { @@ -386,6 +389,7 @@ target_ulong helper_mfhc0_saar(CPUMIPSState *env) } return 0; } +#endif target_ulong helper_mftc0_entryhi(CPUMIPSState *env) { @@ -514,6 +518,7 @@ target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) return env->CP0_WatchHi[sel]; } +#ifdef CONFIG_MIPS_ITU target_ulong helper_dmfc0_saar(CPUMIPSState *env) { if ((env->CP0_SAARI & 0x3f) < 2) { @@ -521,6 +526,7 @@ target_ulong helper_dmfc0_saar(CPUMIPSState *env) } return 0; } +#endif #endif /* TARGET_MIPS64 */ void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) @@ -1100,6 +1106,7 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) cpu_mips_store_count(env, arg1); } +#ifdef CONFIG_MIPS_ITU void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) { uint32_t target = arg1 & 0x3f; @@ -1139,6 +1146,7 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) } } } +#endif void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 12094cc1e7c..b130222708b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -49,6 +49,16 @@ #ifdef CONFIG_USER_ONLY STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg) #endif +#if defined CONFIG_SYSTEM_ONLY && !defined CONFIG_MIPS_ITU +STUB_HELPER(mfc0_saar, TCGv ret, TCGv_env env) +STUB_HELPER(mfhc0_saar, TCGv ret, TCGv_env env) +STUB_HELPER(mtc0_saari, TCGv_env env, TCGv val) +STUB_HELPER(mtc0_saar, TCGv_env env, TCGv val) +STUB_HELPER(mthc0_saar, TCGv_env env, TCGv val) +#ifdef TARGET_MIPS64 +STUB_HELPER(dmfc0_saar, TCGv ret, TCGv_env env) +#endif +#endif enum { /* indirect opcode tables */