Message ID | 20240124121607.698469-1-vadim.shakirov@syntacore.com |
---|---|
State | New |
Headers | show |
Series | target/riscv/csr: Added the ability to delegate LCOFI to VS | expand |
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1ddc03ff39..ec55be3c45 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1133,7 +1133,7 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, static const uint64_t delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; static const uint64_t vs_delegable_ints = - (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP; + VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
In the AIA specification in the paragraph "Virtual interrupts for VS level" it is indicated for interrupts 13-63: if the bit in hideleg is enabled, then the corresponding vsip and vsie bits are aliases to sip and sie Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com> --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)