| Message ID | 20240117151238.93323-2-npiggin@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/6] target/ppc: Fix 440 tlbwe TLB invalidation gaps | expand |
On 1/17/24 16:12, Nicholas Piggin wrote: > Flushing the TCG TLB pages that cache a software TLB is a common > operation, factor it into its own function. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > target/ppc/mmu_helper.c | 24 +++++++++++++----------- > 1 file changed, 13 insertions(+), 11 deletions(-) > > diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c > index c140f3c96d..949ae87f4f 100644 > --- a/target/ppc/mmu_helper.c > +++ b/target/ppc/mmu_helper.c > @@ -749,12 +749,20 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry) > return ret; > } > > +static void ppcemb_tlb_flush(CPUState *cs, ppcemb_tlb_t *tlb) > +{ > + target_ulong ea; > + > + for (ea = tlb->EPN; ea < tlb->EPN + tlb->size; ea += TARGET_PAGE_SIZE) { > + tlb_flush_page(cs, ea); > + } > +} > + > void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, > target_ulong val) > { > CPUState *cs = env_cpu(env); > ppcemb_tlb_t *tlb; > - target_ulong page, end; > > qemu_log_mask(CPU_LOG_MMU, "%s entry %d val " TARGET_FMT_lx "\n", > __func__, (int)entry, > @@ -763,13 +771,10 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, > tlb = &env->tlb.tlbe[entry]; > /* Invalidate previous TLB (if it's valid) */ > if (tlb->prot & PAGE_VALID) { > - end = tlb->EPN + tlb->size; > qemu_log_mask(CPU_LOG_MMU, "%s: invalidate old TLB %d start " > TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, > - (int)entry, tlb->EPN, end); > - for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { > - tlb_flush_page(cs, page); > - } > + (int)entry, tlb->EPN, tlb->EPN + tlb->size); > + ppcemb_tlb_flush(cs, tlb); > } > tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT) > & PPC4XX_TLBHI_SIZE_MASK); > @@ -805,13 +810,10 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, > tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); > /* Invalidate new TLB (if valid) */ > if (tlb->prot & PAGE_VALID) { > - end = tlb->EPN + tlb->size; > qemu_log_mask(CPU_LOG_MMU, "%s: invalidate TLB %d start " > TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, > - (int)entry, tlb->EPN, end); > - for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { > - tlb_flush_page(cs, page); > - } > + (int)entry, tlb->EPN, tlb->EPN + tlb->size); > + ppcemb_tlb_flush(cs, tlb); > } > } >
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index c140f3c96d..949ae87f4f 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -749,12 +749,20 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry) return ret; } +static void ppcemb_tlb_flush(CPUState *cs, ppcemb_tlb_t *tlb) +{ + target_ulong ea; + + for (ea = tlb->EPN; ea < tlb->EPN + tlb->size; ea += TARGET_PAGE_SIZE) { + tlb_flush_page(cs, ea); + } +} + void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, target_ulong val) { CPUState *cs = env_cpu(env); ppcemb_tlb_t *tlb; - target_ulong page, end; qemu_log_mask(CPU_LOG_MMU, "%s entry %d val " TARGET_FMT_lx "\n", __func__, (int)entry, @@ -763,13 +771,10 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, tlb = &env->tlb.tlbe[entry]; /* Invalidate previous TLB (if it's valid) */ if (tlb->prot & PAGE_VALID) { - end = tlb->EPN + tlb->size; qemu_log_mask(CPU_LOG_MMU, "%s: invalidate old TLB %d start " TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, - (int)entry, tlb->EPN, end); - for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(cs, page); - } + (int)entry, tlb->EPN, tlb->EPN + tlb->size); + ppcemb_tlb_flush(cs, tlb); } tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT) & PPC4XX_TLBHI_SIZE_MASK); @@ -805,13 +810,10 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); /* Invalidate new TLB (if valid) */ if (tlb->prot & PAGE_VALID) { - end = tlb->EPN + tlb->size; qemu_log_mask(CPU_LOG_MMU, "%s: invalidate TLB %d start " TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__, - (int)entry, tlb->EPN, end); - for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(cs, page); - } + (int)entry, tlb->EPN, tlb->EPN + tlb->size); + ppcemb_tlb_flush(cs, tlb); } }
Flushing the TCG TLB pages that cache a software TLB is a common operation, factor it into its own function. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- target/ppc/mmu_helper.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-)