diff mbox series

[v2,3/7] target/ppc: Fix move-to timebase SPR access permissions

Message ID 20231124064001.198572-4-npiggin@gmail.com
State New
Headers show
Series ppc: pnv ChipTOD and various timebase fixes | expand

Commit Message

Nicholas Piggin Nov. 24, 2023, 6:39 a.m. UTC 
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/helper_regs.c | 31 +++++++++++++++++++++++--------
 1 file changed, 23 insertions(+), 8 deletions(-)

Comments

Cédric Le Goater Nov. 24, 2023, 7:12 a.m. UTC | #1 
On 11/24/23 07:39, Nicholas Piggin wrote:
> The move-to timebase registers TBU and TBL can not be read, and they
> can not be written in supervisor mode on hypervisor-capable CPUs.
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>


Reviewed-by: Cédric Le Goater <clg@kaod.org>

Thanks,

C.


> ---
>   target/ppc/helper_regs.c | 31 +++++++++++++++++++++++--------
>   1 file changed, 23 insertions(+), 8 deletions(-)
> 
> diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
> index 6f190ab13b..f1493ddca0 100644
> --- a/target/ppc/helper_regs.c
> +++ b/target/ppc/helper_regs.c
> @@ -468,18 +468,33 @@ void register_generic_sprs(PowerPCCPU *cpu)
>                    &spr_read_tbl, SPR_NOACCESS,
>                    &spr_read_tbl, SPR_NOACCESS,
>                    0x00000000);
> -    spr_register(env, SPR_WR_TBL, "TBL",
> -                 &spr_read_tbl, SPR_NOACCESS,
> -                 &spr_read_tbl, &spr_write_tbl,
> -                 0x00000000);
>       spr_register(env, SPR_TBU, "TBU",
>                    &spr_read_tbu, SPR_NOACCESS,
>                    &spr_read_tbu, SPR_NOACCESS,
>                    0x00000000);
> -    spr_register(env, SPR_WR_TBU, "TBU",
> -                 &spr_read_tbu, SPR_NOACCESS,
> -                 &spr_read_tbu, &spr_write_tbu,
> -                 0x00000000);
> +#ifndef CONFIG_USER_ONLY
> +    if (env->has_hv_mode) {
> +        spr_register_hv(env, SPR_WR_TBL, "TBL",
> +                        SPR_NOACCESS, SPR_NOACCESS,
> +                        SPR_NOACCESS, SPR_NOACCESS,
> +                        SPR_NOACCESS, &spr_write_tbl,
> +                        0x00000000);
> +        spr_register_hv(env, SPR_WR_TBU, "TBU",
> +                        SPR_NOACCESS, SPR_NOACCESS,
> +                        SPR_NOACCESS, SPR_NOACCESS,
> +                        SPR_NOACCESS, &spr_write_tbu,
> +                        0x00000000);
> +    } else {
> +        spr_register(env, SPR_WR_TBL, "TBL",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     SPR_NOACCESS, &spr_write_tbl,
> +                     0x00000000);
> +        spr_register(env, SPR_WR_TBU, "TBU",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     SPR_NOACCESS, &spr_write_tbu,
> +                     0x00000000);
> +    }
> +#endif
>   }
>   
>   void register_non_embedded_sprs(CPUPPCState *env)
diff mbox series

Patch

diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 6f190ab13b..f1493ddca0 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -468,18 +468,33 @@  void register_generic_sprs(PowerPCCPU *cpu)
                  &spr_read_tbl, SPR_NOACCESS,
                  &spr_read_tbl, SPR_NOACCESS,
                  0x00000000);
-    spr_register(env, SPR_WR_TBL, "TBL",
-                 &spr_read_tbl, SPR_NOACCESS,
-                 &spr_read_tbl, &spr_write_tbl,
-                 0x00000000);
     spr_register(env, SPR_TBU, "TBU",
                  &spr_read_tbu, SPR_NOACCESS,
                  &spr_read_tbu, SPR_NOACCESS,
                  0x00000000);
-    spr_register(env, SPR_WR_TBU, "TBU",
-                 &spr_read_tbu, SPR_NOACCESS,
-                 &spr_read_tbu, &spr_write_tbu,
-                 0x00000000);
+#ifndef CONFIG_USER_ONLY
+    if (env->has_hv_mode) {
+        spr_register_hv(env, SPR_WR_TBL, "TBL",
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, &spr_write_tbl,
+                        0x00000000);
+        spr_register_hv(env, SPR_WR_TBU, "TBU",
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        SPR_NOACCESS, &spr_write_tbu,
+                        0x00000000);
+    } else {
+        spr_register(env, SPR_WR_TBL, "TBL",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     SPR_NOACCESS, &spr_write_tbl,
+                     0x00000000);
+        spr_register(env, SPR_WR_TBU, "TBU",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     SPR_NOACCESS, &spr_write_tbu,
+                     0x00000000);
+    }
+#endif
 }
 
 void register_non_embedded_sprs(CPUPPCState *env)