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[60.240.124.93]) by smtp.gmail.com with ESMTPSA id e4-20020a170902d38400b001cc1dff5b86sm1009070pld.244.2023.11.23.02.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 02:30:29 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= , qemu-devel@nongnu.org Subject: [PATCH 1/7] target/ppc: Rename TBL to TB on 64-bit Date: Thu, 23 Nov 2023 20:30:12 +1000 Message-ID: <20231123103018.172383-2-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231123103018.172383-1-npiggin@gmail.com> References: <20231123103018.172383-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From the earliest PowerPC ISA, TBR (later SPR) 268 has been called TB and accessed with mftb instruction. The problem is that TB is the name of the 64-bit register, and 32-bit implementations can only read the lower half with one instruction, so 268 has also been called TBL and it does only read TBL on 32-bit. Change SPR 268 to be called TB on 64-bit implementations. Signed-off-by: Nicholas Piggin --- target/ppc/helper_regs.c | 4 ++++ target/ppc/ppc-qmp-cmds.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index f380342d4d..8c00ed8c06 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -460,7 +460,11 @@ void register_generic_sprs(PowerPCCPU *cpu) } /* Time base */ +#if defined(TARGET_PPC64) + spr_register(env, SPR_VTBL, "TB", +#else spr_register(env, SPR_VTBL, "TBL", +#endif &spr_read_tbl, SPR_NOACCESS, &spr_read_tbl, SPR_NOACCESS, 0x00000000); diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c index f9acc21056..ffaff59e78 100644 --- a/target/ppc/ppc-qmp-cmds.c +++ b/target/ppc/ppc-qmp-cmds.c @@ -103,7 +103,11 @@ const MonitorDef monitor_defs[] = { { "xer", 0, &monitor_get_xer }, { "msr", offsetof(CPUPPCState, msr) }, { "tbu", 0, &monitor_get_tbu, }, +#if defined(TARGET_PPC64) + { "tb", 0, &monitor_get_tbl, }, +#else { "tbl", 0, &monitor_get_tbl, }, +#endif { NULL }, };