| Message ID | 20231102003424.2003428-3-alistair.francis@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: OpenTitan: Fixup ePMP and SPI interrupts | expand |
On 11/1/23 21:34, Alistair Francis wrote: > Set the Ibex CPU priv to 1.12.0 to ensure that smepmp/epmp is correctly > enabled. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ac4a6c7eec..b37b9107cd 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -595,7 +595,7 @@ static void rv32_ibex_cpu_init(Object *obj) > RISCVCPU *cpu = RISCV_CPU(obj); > > riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > - env->priv_ver = PRIV_VERSION_1_11_0; > + env->priv_ver = PRIV_VERSION_1_12_0; > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..b37b9107cd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -595,7 +595,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - env->priv_ver = PRIV_VERSION_1_11_0; + env->priv_ver = PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif
Set the Ibex CPU priv to 1.12.0 to ensure that smepmp/epmp is correctly enabled. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)