| Message ID | 20231101204204.345470-6-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | rv64i CPU, RVA22U64 profile support | expand |
On Wed, Nov 01, 2023 at 05:41:50PM -0300, Daniel Henrique Barboza wrote: > We'll add a new bare CPU type that won't have any default priv_ver. This > means that the CPU will default to priv_ver = 0, i.e. 1.10.0. > > At the same we'll allow these CPUs to enable extensions at will, but > then, if the extension has a priv_ver newer than 1.10, we'll end up > disabling it. Users will then need to manually set priv_ver to something > other than 1.10 to enable the extensions they want, which is not ideal. > > Change the setter() of multi letter extensions to allow user enabled > extensions to bump the priv_ver of the CPU. This will make it > conveniente for users to enable extensions for CPUs that doesn't set a > default priv_ver. > > This change does not affect any existing CPU: vendor CPUs does not allow > extensions to be enabled, and generic CPUs are already set to priv_ver > LATEST. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/tcg/tcg-cpu.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index f54069d06f..b88fce98a4 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -114,6 +114,22 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) > g_assert_not_reached(); > } > > +static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, > + uint32_t ext_offset) > +{ > + int ext_priv_ver; > + > + if (env->priv_ver == PRIV_VERSION_LATEST) { > + return; > + } > + > + ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); > + > + if (env->priv_ver < ext_priv_ver) { > + env->priv_ver = ext_priv_ver; > + } This will ignore user input. If the user, for example, does -cpu rv64,priv_spec=v1.10.0,zicbom=on then, afaict, priv_spec will be silently bumped to 1.12. I think we should error out in that case instead. And, we should also error out for -cpu rv64,zicbom=on,priv_spec=v1.10.0 which means we should know when priv_spec is either - its default value - has been bumped by an extension - has been explicitly set by the user > +} > + > static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, > bool value) > { > @@ -829,6 +845,10 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, > return; > } > > + if (value) { > + cpu_validate_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); > + } Some misa extensions also have priv spec version dependencies. See riscv_cpu_validate_misa_priv() > + > isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); > } > > -- > 2.41.0 > Thanks, drew
On 11/2/23 06:47, Andrew Jones wrote: > On Wed, Nov 01, 2023 at 05:41:50PM -0300, Daniel Henrique Barboza wrote: >> We'll add a new bare CPU type that won't have any default priv_ver. This >> means that the CPU will default to priv_ver = 0, i.e. 1.10.0. >> >> At the same we'll allow these CPUs to enable extensions at will, but >> then, if the extension has a priv_ver newer than 1.10, we'll end up >> disabling it. Users will then need to manually set priv_ver to something >> other than 1.10 to enable the extensions they want, which is not ideal. >> >> Change the setter() of multi letter extensions to allow user enabled >> extensions to bump the priv_ver of the CPU. This will make it >> conveniente for users to enable extensions for CPUs that doesn't set a >> default priv_ver. >> >> This change does not affect any existing CPU: vendor CPUs does not allow >> extensions to be enabled, and generic CPUs are already set to priv_ver >> LATEST. >> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >> --- >> target/riscv/tcg/tcg-cpu.c | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> >> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c >> index f54069d06f..b88fce98a4 100644 >> --- a/target/riscv/tcg/tcg-cpu.c >> +++ b/target/riscv/tcg/tcg-cpu.c >> @@ -114,6 +114,22 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) >> g_assert_not_reached(); >> } >> >> +static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, >> + uint32_t ext_offset) >> +{ >> + int ext_priv_ver; >> + >> + if (env->priv_ver == PRIV_VERSION_LATEST) { >> + return; >> + } >> + >> + ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); >> + >> + if (env->priv_ver < ext_priv_ver) { >> + env->priv_ver = ext_priv_ver; >> + } > > This will ignore user input. If the user, for example, does > > -cpu rv64,priv_spec=v1.10.0,zicbom=on This won't ignore user input because "priv_spec=v1.10.0" will be evaluated during finalize() time, in riscv_cpu_validate_priv_spec(). This change I made was made with this behavior in mind. In the case you mentioned, this will happen: $ ./build/qemu-system-riscv64 -M virt -cpu rv64,priv_spec=v1.10.0,zicbom=on qemu-system-riscv64: H extension requires priv spec 1.12.0 This happened because, although 'zicbom=true' would bump priv ver to 1.12.0 if needed (it isn't - rv64 is already set to LATEST), "priv_spec=v1.10.0" is evaluated during finalize() time and the CPU priv_ver is set to 1.10 before our validation step. This means that doesn't matter where the 'priv_spec' option is in the command line, it'll always be honored. > > then, afaict, priv_spec will be silently bumped to 1.12. I think we should > error out in that case instead. And, we should also error out for > > -cpu rv64,zicbom=on,priv_spec=v1.10.0 > > which means we should know when priv_spec is either > > - its default value > - has been bumped by an extension > - has been explicitly set by the user > >> +} >> + >> static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, >> bool value) >> { >> @@ -829,6 +845,10 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, >> return; >> } >> >> + if (value) { >> + cpu_validate_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); >> + } > > Some misa extensions also have priv spec version dependencies. See > riscv_cpu_validate_misa_priv() Yeah. I'll add this same mechanic to RVH, the only MISA bit we have that has a priv_ver limitation. Thanks, Daniel > >> + >> isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); >> } >> >> -- >> 2.41.0 >> > > Thanks, > drew
On Thu, Nov 02, 2023 at 10:42:25AM -0300, Daniel Henrique Barboza wrote: > > > On 11/2/23 06:47, Andrew Jones wrote: > > On Wed, Nov 01, 2023 at 05:41:50PM -0300, Daniel Henrique Barboza wrote: > > > We'll add a new bare CPU type that won't have any default priv_ver. This > > > means that the CPU will default to priv_ver = 0, i.e. 1.10.0. > > > > > > At the same we'll allow these CPUs to enable extensions at will, but > > > then, if the extension has a priv_ver newer than 1.10, we'll end up > > > disabling it. Users will then need to manually set priv_ver to something > > > other than 1.10 to enable the extensions they want, which is not ideal. > > > > > > Change the setter() of multi letter extensions to allow user enabled > > > extensions to bump the priv_ver of the CPU. This will make it > > > conveniente for users to enable extensions for CPUs that doesn't set a > > > default priv_ver. > > > > > > This change does not affect any existing CPU: vendor CPUs does not allow > > > extensions to be enabled, and generic CPUs are already set to priv_ver > > > LATEST. > > > > > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > > > --- > > > target/riscv/tcg/tcg-cpu.c | 20 ++++++++++++++++++++ > > > 1 file changed, 20 insertions(+) > > > > > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > > > index f54069d06f..b88fce98a4 100644 > > > --- a/target/riscv/tcg/tcg-cpu.c > > > +++ b/target/riscv/tcg/tcg-cpu.c > > > @@ -114,6 +114,22 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) > > > g_assert_not_reached(); > > > } > > > +static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, > > > + uint32_t ext_offset) > > > +{ > > > + int ext_priv_ver; > > > + > > > + if (env->priv_ver == PRIV_VERSION_LATEST) { > > > + return; > > > + } > > > + > > > + ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); > > > + > > > + if (env->priv_ver < ext_priv_ver) { > > > + env->priv_ver = ext_priv_ver; > > > + } > > > > This will ignore user input. If the user, for example, does > > > > -cpu rv64,priv_spec=v1.10.0,zicbom=on > > > This won't ignore user input because "priv_spec=v1.10.0" will be evaluated during > finalize() time, in riscv_cpu_validate_priv_spec(). This change I made was made > with this behavior in mind. > > In the case you mentioned, this will happen: > > $ ./build/qemu-system-riscv64 -M virt -cpu rv64,priv_spec=v1.10.0,zicbom=on > qemu-system-riscv64: H extension requires priv spec 1.12.0 > > This happened because, although 'zicbom=true' would bump priv ver to 1.12.0 if needed > (it isn't - rv64 is already set to LATEST), "priv_spec=v1.10.0" is evaluated during > finalize() time and the CPU priv_ver is set to 1.10 before our validation step. > > This means that doesn't matter where the 'priv_spec' option is in the command line, > it'll always be honored. Oh, good. Sorry for the noise! But maybe a comment above the priv_ver bump saying something along the lines of what you wrote here would help ease the minds of those that cross this in the future (including the mind of my future self after I've forgotten this again) > > > > > > then, afaict, priv_spec will be silently bumped to 1.12. I think we should > > error out in that case instead. And, we should also error out for > > > > -cpu rv64,zicbom=on,priv_spec=v1.10.0 > > > > which means we should know when priv_spec is either > > > > - its default value > > - has been bumped by an extension > > - has been explicitly set by the user > > > > > > +} > > > + > > > static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, > > > bool value) > > > { > > > @@ -829,6 +845,10 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, > > > return; > > > } > > > + if (value) { > > > + cpu_validate_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); > > > + } > > > > Some misa extensions also have priv spec version dependencies. See > > riscv_cpu_validate_misa_priv() > > Yeah. I'll add this same mechanic to RVH, the only MISA bit we have that has a priv_ver > limitation. Thanks, Thanks, drew
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f54069d06f..b88fce98a4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -114,6 +114,22 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) g_assert_not_reached(); } +static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env, + uint32_t ext_offset) +{ + int ext_priv_ver; + + if (env->priv_ver == PRIV_VERSION_LATEST) { + return; + } + + ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); + + if (env->priv_ver < ext_priv_ver) { + env->priv_ver = ext_priv_ver; + } +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -829,6 +845,10 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, return; } + if (value) { + cpu_validate_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); + } + isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); }
We'll add a new bare CPU type that won't have any default priv_ver. This means that the CPU will default to priv_ver = 0, i.e. 1.10.0. At the same we'll allow these CPUs to enable extensions at will, but then, if the extension has a priv_ver newer than 1.10, we'll end up disabling it. Users will then need to manually set priv_ver to something other than 1.10 to enable the extensions they want, which is not ideal. Change the setter() of multi letter extensions to allow user enabled extensions to bump the priv_ver of the CPU. This will make it conveniente for users to enable extensions for CPUs that doesn't set a default priv_ver. This change does not affect any existing CPU: vendor CPUs does not allow extensions to be enabled, and generic CPUs are already set to priv_ver LATEST. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/tcg/tcg-cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)