| Message ID | 20231026151828.754279-6-max.chou@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | Update RISC-V vector crypto to ratified v1.0.0 | expand |
On 10/26/23 12:18, Max Chou wrote: > Signed-off-by: Max Chou <max.chou@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 5099c786415..992f8e0f7b0 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -125,6 +125,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), > ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), > ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), > + ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), > ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), > ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), > ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), > @@ -1370,6 +1371,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > /* Vector cryptography extensions */ > MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false), > MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false), > + MULTI_EXT_CFG_BOOL("x-zvkb", ext_zvkg, false), > MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false), > MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false), > MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
On Fri, Oct 27, 2023 at 1:21 AM Max Chou <max.chou@sifive.com> wrote: > > Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 5099c786415..992f8e0f7b0 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -125,6 +125,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), > ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), > ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), > + ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), > ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), > ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), > ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), > @@ -1370,6 +1371,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > /* Vector cryptography extensions */ > MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false), > MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false), > + MULTI_EXT_CFG_BOOL("x-zvkb", ext_zvkg, false), > MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false), > MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false), > MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false), > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5099c786415..992f8e0f7b0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -125,6 +125,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), @@ -1370,6 +1371,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { /* Vector cryptography extensions */ MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false), MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false), + MULTI_EXT_CFG_BOOL("x-zvkb", ext_zvkg, false), MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false), MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false), MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false),
Signed-off-by: Max Chou <max.chou@sifive.com> --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+)