| Message ID | 20230927093552.493279-1-kbastian@mail.uni-paderborn.de |
|---|---|
| State | New |
| Headers | show |
On Wed, Sep 27, 2023 at 11:35:31AM +0200, Bastian Koppelmann wrote: > The following changes since commit 11a629d246e4e7785a6f0efb99bd15a32c04feda: > > Merge tag 'pull-nbd-2023-09-25' of https://repo.or.cz/qemu/ericb into staging (2023-09-26 09:04:23 -0400) > > are available in the Git repository at: > > https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230927 > > for you to fetch changes up to 32dd1f0b4bf5f38f37434b0c8fe6c8d86e093b2b: > > target/tricore: Change effective address (ea) to target_ulong (2023-09-27 11:22:42 +0200) > > ---------------------------------------------------------------- > - Add FTOU, CRCN, FTOHP, and HPTOF insns > - Add test for arithmetic TriCore insns > > ---------------------------------------------------------------- > Bastian Koppelmann (21): > tests/tcg/tricore: Bump cpu to tc37x > target/tricore: Implement CRCN insn > target/tricore: Correctly handle FPU RM from PSW > target/tricore: Implement FTOU insn > target/tricore: Clarify special case for FTOUZ insn > target/tricore: Implement ftohp insn > target/tricore: Implement hptof insn > target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 > target/tricore: Swap src and dst reg for RCRR_INSERT > target/tricore: Replace cpu_*_code with translator_* > target/tricore: Fix FTOUZ being ISA v1.3.1 up > tests/tcg/tricore: Extended and non-extened regs now match > hw/tricore: Log failing test in testdevice > tests/tcg: Reset result register after each test > tests/tcg/tricore: Add test for all arith insns up to addx > tests/tcg/tricore: Add test from 'and' to 'csub' > tests/tcg/tricore: Add test from 'dextr' to 'lt' > tests/tcg/tricore: Add test from 'max' to 'shas' > tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' > target/tricore: Remove CSFRs from cpu.h > target/tricore: Change effective address (ea) to target_ulong > > hw/tricore/tricore_testdevice.c | 4 + > target/tricore/cpu.h | 143 +-------------- > target/tricore/fpu_helper.c | 111 ++++++++++++ > target/tricore/helper.c | 19 +- > target/tricore/helper.h | 4 + > target/tricore/op_helper.c | 79 ++++++++- > target/tricore/translate.c | 56 ++++-- > target/tricore/tricore-opcodes.h | 3 + > tests/tcg/tricore/Makefile.softmmu-target | 7 +- > tests/tcg/tricore/asm/macros.h | 190 +++++++++++++++++--- > tests/tcg/tricore/asm/sas.py | 21 +++ Don't merge this one. Somehow a file slipped in, that should not have been in the merge. Sorry for the inconvenience. I'll respin. Cheers, Bastian
The following changes since commit 11a629d246e4e7785a6f0efb99bd15a32c04feda: Merge tag 'pull-nbd-2023-09-25' of https://repo.or.cz/qemu/ericb into staging (2023-09-26 09:04:23 -0400) are available in the Git repository at: https://github.com/bkoppelmann/qemu.git tags/pull-tricore-20230927 for you to fetch changes up to 32dd1f0b4bf5f38f37434b0c8fe6c8d86e093b2b: target/tricore: Change effective address (ea) to target_ulong (2023-09-27 11:22:42 +0200) ---------------------------------------------------------------- - Add FTOU, CRCN, FTOHP, and HPTOF insns - Add test for arithmetic TriCore insns ---------------------------------------------------------------- Bastian Koppelmann (21): tests/tcg/tricore: Bump cpu to tc37x target/tricore: Implement CRCN insn target/tricore: Correctly handle FPU RM from PSW target/tricore: Implement FTOU insn target/tricore: Clarify special case for FTOUZ insn target/tricore: Implement ftohp insn target/tricore: Implement hptof insn target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 target/tricore: Swap src and dst reg for RCRR_INSERT target/tricore: Replace cpu_*_code with translator_* target/tricore: Fix FTOUZ being ISA v1.3.1 up tests/tcg/tricore: Extended and non-extened regs now match hw/tricore: Log failing test in testdevice tests/tcg: Reset result register after each test tests/tcg/tricore: Add test for all arith insns up to addx tests/tcg/tricore: Add test from 'and' to 'csub' tests/tcg/tricore: Add test from 'dextr' to 'lt' tests/tcg/tricore: Add test from 'max' to 'shas' tests/tcg/tricore: Add test from 'shuffle' to 'xor.t' target/tricore: Remove CSFRs from cpu.h target/tricore: Change effective address (ea) to target_ulong hw/tricore/tricore_testdevice.c | 4 + target/tricore/cpu.h | 143 +-------------- target/tricore/fpu_helper.c | 111 ++++++++++++ target/tricore/helper.c | 19 +- target/tricore/helper.h | 4 + target/tricore/op_helper.c | 79 ++++++++- target/tricore/translate.c | 56 ++++-- target/tricore/tricore-opcodes.h | 3 + tests/tcg/tricore/Makefile.softmmu-target | 7 +- tests/tcg/tricore/asm/macros.h | 190 +++++++++++++++++--- tests/tcg/tricore/asm/sas.py | 21 +++ tests/tcg/tricore/asm/test_arith.S | 280 ++++++++++++++++++++++++++++++ tests/tcg/tricore/asm/test_crcn.S | 9 + tests/tcg/tricore/asm/test_ftohp.S | 14 ++ tests/tcg/tricore/asm/test_ftou.S | 12 ++ tests/tcg/tricore/asm/test_hptof.S | 12 ++ tests/tcg/tricore/asm/test_insert.S | 14 ++ 17 files changed, 801 insertions(+), 177 deletions(-) create mode 100644 tests/tcg/tricore/asm/sas.py create mode 100644 tests/tcg/tricore/asm/test_arith.S create mode 100644 tests/tcg/tricore/asm/test_crcn.S create mode 100644 tests/tcg/tricore/asm/test_ftohp.S create mode 100644 tests/tcg/tricore/asm/test_ftou.S create mode 100644 tests/tcg/tricore/asm/test_hptof.S