diff mbox series

[RFC,2/3] target/ppc: Use FP CR1 update helper more widely

Message ID 20230913005814.413113-3-npiggin@gmail.com
State New
Headers show
Series target/ppc: Change CR registers from i32 to tl | expand

Commit Message

Nicholas Piggin Sept. 13, 2023, 12:58 a.m. UTC
Several places open-code this FP CR1 update. Move them to call
gen_set_cr1_from_fpscr().

FPSCR_OX = 28 so move that to the symbolic constant while we are here.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/translate/fp-impl.c.inc | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

Comments

Philippe Mathieu-Daudé Sept. 13, 2023, 6:19 a.m. UTC | #1
On 13/9/23 02:58, Nicholas Piggin wrote:
> Several places open-code this FP CR1 update. Move them to call
> gen_set_cr1_from_fpscr().
> 
> FPSCR_OX = 28 so move that to the symbolic constant while we are here.
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>   target/ppc/translate/fp-impl.c.inc | 16 ++++++----------
>   1 file changed, 6 insertions(+), 10 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 4e355cb379..9f71c039ce 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -20,12 +20,12 @@  static void gen_set_cr1_from_fpscr(DisasContext *ctx)
 {
     TCGv tmp = tcg_temp_new();
     tcg_gen_mov_tl(tmp, cpu_fpscr);
-    tcg_gen_shri_tl(cpu_crf[1], tmp, 28);
+    tcg_gen_shri_tl(cpu_crf[1], tmp, FPSCR_OX);
 }
 #else
 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
 {
-    tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
+    tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, FPSCR_OX);
 }
 #endif
 
@@ -694,8 +694,7 @@  static void gen_mtfsb0(DisasContext *ctx)
         gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb));
     }
     if (unlikely(Rc(ctx->opcode) != 0)) {
-        tcg_gen_mov_tl(cpu_crf[1], cpu_fpscr);
-        tcg_gen_shri_tl(cpu_crf[1], cpu_crf[1], FPSCR_OX);
+        gen_set_cr1_from_fpscr(ctx);
     }
 }
 
@@ -714,8 +713,7 @@  static void gen_mtfsb1(DisasContext *ctx)
         gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb));
     }
     if (unlikely(Rc(ctx->opcode) != 0)) {
-        tcg_gen_mov_tl(cpu_crf[1], cpu_fpscr);
-        tcg_gen_shri_tl(cpu_crf[1], cpu_crf[1], FPSCR_OX);
+        gen_set_cr1_from_fpscr(ctx);
     }
     /* We can raise a deferred exception */
     gen_helper_fpscr_check_status(cpu_env);
@@ -750,8 +748,7 @@  static void gen_mtfsf(DisasContext *ctx)
     get_fpr(t1, rB(ctx->opcode));
     gen_helper_store_fpscr(cpu_env, t1, t0);
     if (unlikely(Rc(ctx->opcode) != 0)) {
-        tcg_gen_mov_tl(cpu_crf[1], cpu_fpscr);
-        tcg_gen_shri_tl(cpu_crf[1], cpu_crf[1], FPSCR_OX);
+        gen_set_cr1_from_fpscr(ctx);
     }
     /* We can raise a deferred exception */
     gen_helper_fpscr_check_status(cpu_env);
@@ -779,8 +776,7 @@  static void gen_mtfsfi(DisasContext *ctx)
     t1 = tcg_constant_i32(1 << sh);
     gen_helper_store_fpscr(cpu_env, t0, t1);
     if (unlikely(Rc(ctx->opcode) != 0)) {
-        tcg_gen_mov_tl(cpu_crf[1], cpu_fpscr);
-        tcg_gen_shri_tl(cpu_crf[1], cpu_crf[1], FPSCR_OX);
+        gen_set_cr1_from_fpscr(ctx);
     }
     /* We can raise a deferred exception */
     gen_helper_fpscr_check_status(cpu_env);