| Message ID | 20230627092631.22286-1-jason.chien@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | [RFC] target/riscv: Add Zihintntl extension ISA string to DTS | expand |
On 6/27/23 06:26, Jason Chien wrote: > RVA23 Profiles states: > The RVA23 profiles are intended to be used for 64-bit application > processors that will run rich OS stacks from standard binary OS > distributions and with a substantial number of third-party binary user > applications that will be supported over a considerable length of time > in the field. > > The chapter 4 of the unprivileged spec introduces the Zihintntl extension > and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose > targeting software stacks includes Linux. Thus the DTS should contain > the Zihintntl ISA string in order to pass to Linux. > > The unprivileged spec states: > Like any HINTs, these instructions may be freely ignored. Hence, although > they are described in terms of cache-based memory hierarchies, they do not > mandate the provision of caches. > > These instructions are encoded with used opcode, which QEMU already > supports, and QEMU does not emulate cache, therefore we just need to add > a new property for the extension. > > Signed-off-by: Jason Chien <jason.chien@sifive.com> > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 881bddf393..aa99781f17 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -81,6 +81,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), > ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), > + ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), > ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), > ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), > ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), > @@ -1598,6 +1599,7 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > + DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, false), IIUC we want to add the possibility of enabling zihintntl (and add it to riscv,isa DT) because it's mandatory for RVA23. And zihintntl can be considered a no-op (i.e. can be enabled at will) because (1) we don't emulate cache and (2) applications If that's the case, I'd say to make it default to 'true' then. It would be one less extension to worry about to enable the RVA23 profile in QEMU. Thanks, Daniel > DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), > DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), > DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index c4a627d335..c7da2facef 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -66,6 +66,7 @@ struct RISCVCPUConfig { > bool ext_icbom; > bool ext_icboz; > bool ext_zicond; > + bool ext_zihintntl; > bool ext_zihintpause; > bool ext_smstateen; > bool ext_sstc;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 881bddf393..aa99781f17 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -81,6 +81,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), @@ -1598,6 +1599,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, false), DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index c4a627d335..c7da2facef 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -66,6 +66,7 @@ struct RISCVCPUConfig { bool ext_icbom; bool ext_icboz; bool ext_zicond; + bool ext_zihintntl; bool ext_zihintpause; bool ext_smstateen; bool ext_sstc;
RVA23 Profiles states: The RVA23 profiles are intended to be used for 64-bit application processors that will run rich OS stacks from standard binary OS distributions and with a substantial number of third-party binary user applications that will be supported over a considerable length of time in the field. The chapter 4 of the unprivileged spec introduces the Zihintntl extension and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose targeting software stacks includes Linux. Thus the DTS should contain the Zihintntl ISA string in order to pass to Linux. The unprivileged spec states: Like any HINTs, these instructions may be freely ignored. Hence, although they are described in terms of cache-based memory hierarchies, they do not mandate the provision of caches. These instructions are encoded with used opcode, which QEMU already supports, and QEMU does not emulate cache, therefore we just need to add a new property for the extension. Signed-off-by: Jason Chien <jason.chien@sifive.com> --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+)