diff mbox series

[v2,3/4] target/ppc: Remove larx/stcx. memory barrier semantics

Message ID 20230605025445.161932-3-npiggin@gmail.com
State New
Headers show
Series [v2,1/4] target/ppc: Fix lqarx to set cpu_reserve | expand

Commit Message

Nicholas Piggin June 5, 2023, 2:54 a.m. UTC 
larx and stcx. are not defined to order any memory operations.
Remove the barriers.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/translate.c | 11 -----------
 1 file changed, 11 deletions(-)

Comments

Daniel Henrique Barboza June 5, 2023, 1:42 p.m. UTC | #1 
On 6/4/23 23:54, Nicholas Piggin wrote:
> larx and stcx. are not defined to order any memory operations.
> Remove the barriers.
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---

Queued. Thanks,


Daniel

>   target/ppc/translate.c | 11 -----------
>   1 file changed, 11 deletions(-)
> 
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 538f757dec..acb99d8691 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3592,7 +3592,6 @@ static void gen_load_locked(DisasContext *ctx, MemOp memop)
>       tcg_gen_mov_tl(cpu_reserve, t0);
>       tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop));
>       tcg_gen_mov_tl(cpu_reserve_val, gpr);
> -    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
>   }
>   
>   #define LARX(name, memop)                  \
> @@ -3836,11 +3835,6 @@ static void gen_conditional_store(DisasContext *ctx, MemOp memop)
>   
>       gen_set_label(l1);
>   
> -    /*
> -     * Address mismatch implies failure.  But we still need to provide
> -     * the memory barrier semantics of the instruction.
> -     */
> -    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
>       tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
>   
>       gen_set_label(l2);
> @@ -3944,11 +3938,6 @@ static void gen_stqcx_(DisasContext *ctx)
>       tcg_gen_br(lab_over);
>       gen_set_label(lab_fail);
>   
> -    /*
> -     * Address mismatch implies failure.  But we still need to provide
> -     * the memory barrier semantics of the instruction.
> -     */
> -    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
>       tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
>   
>       gen_set_label(lab_over);
diff mbox series

Patch

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 538f757dec..acb99d8691 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3592,7 +3592,6 @@  static void gen_load_locked(DisasContext *ctx, MemOp memop)
     tcg_gen_mov_tl(cpu_reserve, t0);
     tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop));
     tcg_gen_mov_tl(cpu_reserve_val, gpr);
-    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
 }
 
 #define LARX(name, memop)                  \
@@ -3836,11 +3835,6 @@  static void gen_conditional_store(DisasContext *ctx, MemOp memop)
 
     gen_set_label(l1);
 
-    /*
-     * Address mismatch implies failure.  But we still need to provide
-     * the memory barrier semantics of the instruction.
-     */
-    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
 
     gen_set_label(l2);
@@ -3944,11 +3938,6 @@  static void gen_stqcx_(DisasContext *ctx)
     tcg_gen_br(lab_over);
     gen_set_label(lab_fail);
 
-    /*
-     * Address mismatch implies failure.  But we still need to provide
-     * the memory barrier semantics of the instruction.
-     */
-    tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
 
     gen_set_label(lab_over);