@@ -959,6 +959,10 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset,
val = xive->vc_regs[reg];
break;
+ case VC_ESBC_CFG:
+ val = xive->vc_regs[reg];
+ break;
+
/*
* EAS cache updates (not modeled)
*/
@@ -1050,6 +1054,9 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset,
/* ESB update */
break;
+ case VC_ESBC_CFG:
+ break;
+
/*
* EAS cache updates (not modeled)
*/
@@ -232,6 +232,10 @@
#define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35)
#define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */
+/* ESBC configuration */
+#define X_VC_ESBC_CFG 0x148
+#define VC_ESBC_CFG 0x240
+
/* EASC flush control register */
#define X_VC_EASC_FLUSH_CTRL 0x160
#define VC_EASC_FLUSH_CTRL 0x300