diff mbox series

[v2,1/1] target/i386: add support for LAM in CPUID enumeration

Message ID 20230531013250.18311-2-binbin.wu@linux.intel.com
State New
Headers show
Series target/i386: add support for LAM in CPUID enumeration | expand

Commit Message

Binbin Wu May 31, 2023, 1:32 a.m. UTC 
From: Robert Hoo <robert.hu@linux.intel.com>

Linear Address Masking (LAM) is a new Intel CPU feature, which allows software
to use of the untranslated address bits for metadata.

The bit definition:
CPUID.(EAX=7,ECX=1):EAX[26]

Add CPUID definition for LAM.

More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING (LAM)"
https://cdrdv2.intel.com/v1/dl/getContent/671368

Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Co-developed-by: Binbin Wu <binbin.wu@linux.intel.com>
Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com>
---
 target/i386/cpu.c | 2 +-
 target/i386/cpu.h | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

Comments

Xiaoyao Li May 31, 2023, 3:45 a.m. UTC | #1 
On 5/31/2023 9:32 AM, Binbin Wu wrote:
> From: Robert Hoo <robert.hu@linux.intel.com>
> 
> Linear Address Masking (LAM) is a new Intel CPU feature, which allows software
> to use of the untranslated address bits for metadata.
> 
> The bit definition:
> CPUID.(EAX=7,ECX=1):EAX[26]
> 
> Add CPUID definition for LAM.
> 
> More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING (LAM)"
> https://cdrdv2.intel.com/v1/dl/getContent/671368

LAM defines new bits in CR3 and CR4. I think it needs corresponding 
support in QEMU as well.

> Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
> Co-developed-by: Binbin Wu <binbin.wu@linux.intel.com>
> Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com>
> ---
>   target/i386/cpu.c | 2 +-
>   target/i386/cpu.h | 2 ++
>   2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 1242bd541a..f4436b3657 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -881,7 +881,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>               "fsrc", NULL, NULL, NULL,
>               NULL, NULL, NULL, NULL,
>               NULL, "amx-fp16", NULL, "avx-ifma",
> -            NULL, NULL, NULL, NULL,
> +            NULL, NULL, "lam", NULL,
>               NULL, NULL, NULL, NULL,
>           },
>           .cpuid = {
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 7201a71de8..eb800ba2e2 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -924,6 +924,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
>   #define CPUID_7_1_EAX_AMX_FP16          (1U << 21)
>   /* Support for VPMADD52[H,L]UQ */
>   #define CPUID_7_1_EAX_AVX_IFMA          (1U << 23)
> +/* Linear Address Masking */
> +#define CPUID_7_1_EAX_LAM               (1U << 26)
>   
>   /* Support for VPDPB[SU,UU,SS]D[,S] */
>   #define CPUID_7_1_EDX_AVX_VNNI_INT8     (1U << 4)
Binbin Wu June 1, 2023, 3:26 a.m. UTC | #2 
On 5/31/2023 11:45 AM, Xiaoyao Li wrote:
> On 5/31/2023 9:32 AM, Binbin Wu wrote:
>> From: Robert Hoo <robert.hu@linux.intel.com>
>>
>> Linear Address Masking (LAM) is a new Intel CPU feature, which allows 
>> software
>> to use of the untranslated address bits for metadata.
>>
>> The bit definition:
>> CPUID.(EAX=7,ECX=1):EAX[26]
>>
>> Add CPUID definition for LAM.
>>
>> More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING 
>> (LAM)"
>> https://cdrdv2.intel.com/v1/dl/getContent/671368
>
> LAM defines new bits in CR3 and CR4. I think it needs corresponding 
> support in QEMU as well.

In QEMU, there are several callers call cpu_x86_update_{cr3,cr4}().

* target/i386/tcg
   If there is no objection, LAM feature will not be supported for TCG 
of target-i386.
   LAM CPUID bit will not be added to TCG_7_1_EAX_FEATURES.
   helper_write_crN() and helper_vmrun() check CR4 reserved bit before 
calling cpu_x86_update_cr4(),
   i.e. CR4 LAM bit is not allowed to be set in TCG.
   helper_write_crN() and helper_vmrun() check max physcial address bits 
before calling cpu_x86_update_cr3(),
   no change needed, i.e. CR3 LAM bits are not allowed to be set in TCG.
   About CR4 reserved bits, although QEMU code only uses 
cr4_reserved_bits() in target/i386/tcg,
   still want to do the following changes:
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index eb800ba2e2..3946fe5393 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -261,6 +261,7 @@ typedef enum X86Seg {
  #define CR4_SMAP_MASK   (1U << 21)
  #define CR4_PKE_MASK   (1U << 22)
  #define CR4_PKS_MASK   (1U << 24)
+#define CR4_LAM_SUP_MASK (1U << 28)

  #define CR4_RESERVED_MASK \
  (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
@@ -269,7 +270,8 @@ typedef enum X86Seg {
                  | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
                  | CR4_LA57_MASK \
                  | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
-                | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | 
CR4_PKS_MASK))
+                | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | 
CR4_PKS_MASK \
+                | CR4_LAM_SUP_MASK))

  #define DR6_BD          (1 << 13)
  #define DR6_BS          (1 << 14)
@@ -2469,6 +2471,9 @@ static inline uint64_t 
cr4_reserved_bits(CPUX86State *env)
      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
          reserved_bits |= CR4_PKS_MASK;
      }
+    if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) {
+        reserved_bits |= CR4_LAM_SUP_MASK;
+    }
      return reserved_bits;
  }


* target/i386/gdbstub
   x86_cpu_gdb_write_register() will call cpu_x86_update_cr3() to update 
cr3/cr4.
   Allow gdb to set the LAM bit(s) to CR3/CR4, if vcpu doesn't support 
LAM, set sregs will fail in KVM.


* target/i386/cpu
   x86_cpu_reset_hold() will call cpu_x86_update_cr4() to reset cr4, it 
should be OK.


>
>> Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
>> Co-developed-by: Binbin Wu <binbin.wu@linux.intel.com>
>> Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com>
>> ---
>>   target/i386/cpu.c | 2 +-
>>   target/i386/cpu.h | 2 ++
>>   2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 1242bd541a..f4436b3657 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -881,7 +881,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>>               "fsrc", NULL, NULL, NULL,
>>               NULL, NULL, NULL, NULL,
>>               NULL, "amx-fp16", NULL, "avx-ifma",
>> -            NULL, NULL, NULL, NULL,
>> +            NULL, NULL, "lam", NULL,
>>               NULL, NULL, NULL, NULL,
>>           },
>>           .cpuid = {
>> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
>> index 7201a71de8..eb800ba2e2 100644
>> --- a/target/i386/cpu.h
>> +++ b/target/i386/cpu.h
>> @@ -924,6 +924,8 @@ uint64_t 
>> x86_cpu_get_supported_feature_word(FeatureWord w,
>>   #define CPUID_7_1_EAX_AMX_FP16          (1U << 21)
>>   /* Support for VPMADD52[H,L]UQ */
>>   #define CPUID_7_1_EAX_AVX_IFMA          (1U << 23)
>> +/* Linear Address Masking */
>> +#define CPUID_7_1_EAX_LAM               (1U << 26)
>>     /* Support for VPDPB[SU,UU,SS]D[,S] */
>>   #define CPUID_7_1_EDX_AVX_VNNI_INT8     (1U << 4)
>
diff mbox series

Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1242bd541a..f4436b3657 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -881,7 +881,7 @@  FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             "fsrc", NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             NULL, "amx-fp16", NULL, "avx-ifma",
-            NULL, NULL, NULL, NULL,
+            NULL, NULL, "lam", NULL,
             NULL, NULL, NULL, NULL,
         },
         .cpuid = {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7201a71de8..eb800ba2e2 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -924,6 +924,8 @@  uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
 #define CPUID_7_1_EAX_AMX_FP16          (1U << 21)
 /* Support for VPMADD52[H,L]UQ */
 #define CPUID_7_1_EAX_AVX_IFMA          (1U << 23)
+/* Linear Address Masking */
+#define CPUID_7_1_EAX_LAM               (1U << 26)
 
 /* Support for VPDPB[SU,UU,SS]D[,S] */
 #define CPUID_7_1_EDX_AVX_VNNI_INT8     (1U << 4)