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[v2,1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie.

Message ID 20230526162308.22892-2-rkanwal@rivosinc.com
State New
Headers show
Series target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support | expand

Commit Message

Rajnesh Kanwal May 26, 2023, 4:23 p.m. UTC 
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Alistair Francis June 2, 2023, 3:10 a.m. UTC | #1 
On Sat, May 27, 2023 at 2:25 AM Rajnesh Kanwal <rkanwal@rivosinc.com> wrote:
>
> Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4451bd1263..041f0b3e2e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1522,7 +1522,7 @@ static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
>      env->mie = (env->mie & ~mask) | (new_val & mask);
>
>      if (!riscv_has_ext(env, RVH)) {
> -        env->mie &= ~((uint64_t)MIP_SGEIP);
> +        env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS);
>      }
>
>      return RISCV_EXCP_NONE;
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4451bd1263..041f0b3e2e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1522,7 +1522,7 @@  static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
     env->mie = (env->mie & ~mask) | (new_val & mask);
 
     if (!riscv_has_ext(env, RVH)) {
-        env->mie &= ~((uint64_t)MIP_SGEIP);
+        env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS);
     }
 
     return RISCV_EXCP_NONE;