diff mbox series

[v2,4/8] disas/riscv.c: Support disas for Zcm* extensions

Message ID 20230523093539.203909-5-liweiwei@iscas.ac.cn
State New
Headers show
Series Add support for extension specific disas | expand

Commit Message

Weiwei Li May 23, 2023, 9:35 a.m. UTC 
Support disas for Zcmt* instructions only when related extensions
are supported.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 disas/riscv.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

Alistair Francis May 26, 2023, 1:23 a.m. UTC | #1 
On Tue, May 23, 2023 at 7:37 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Support disas for Zcmt* instructions only when related extensions
> are supported.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  disas/riscv.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 729ab684da..49a3eb6ac4 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2501,7 +2501,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                  op = rv_op_c_sqsp;
>              } else {
>                  op = rv_op_c_fsdsp;
> -                if (((inst >> 12) & 0b01)) {
> +                if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
>                      switch ((inst >> 8) & 0b01111) {
>                      case 8:
>                          if (((inst >> 4) & 0b01111) >= 4) {
> @@ -2527,6 +2527,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                  } else {
>                      switch ((inst >> 10) & 0b011) {
>                      case 0:
> +                        if (!dec->cfg->ext_zcmt) {
> +                            break;
> +                        }
>                          if (((inst >> 2) & 0xFF) >= 32) {
>                              op = rv_op_cm_jalt;
>                          } else {
> @@ -2534,6 +2537,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
>                          }
>                          break;
>                      case 3:
> +                        if (!dec->cfg->ext_zcmp) {
> +                            break;
> +                        }
>                          switch ((inst >> 5) & 0b011) {
>                          case 1: op = rv_op_cm_mvsa01; break;
>                          case 3: op = rv_op_cm_mva01s; break;
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/disas/riscv.c b/disas/riscv.c
index 729ab684da..49a3eb6ac4 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2501,7 +2501,7 @@  static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 op = rv_op_c_sqsp;
             } else {
                 op = rv_op_c_fsdsp;
-                if (((inst >> 12) & 0b01)) {
+                if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
                     switch ((inst >> 8) & 0b01111) {
                     case 8:
                         if (((inst >> 4) & 0b01111) >= 4) {
@@ -2527,6 +2527,9 @@  static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 } else {
                     switch ((inst >> 10) & 0b011) {
                     case 0:
+                        if (!dec->cfg->ext_zcmt) {
+                            break;
+                        }
                         if (((inst >> 2) & 0xFF) >= 32) {
                             op = rv_op_cm_jalt;
                         } else {
@@ -2534,6 +2537,9 @@  static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
                         }
                         break;
                     case 3:
+                        if (!dec->cfg->ext_zcmp) {
+                            break;
+                        }
                         switch ((inst >> 5) & 0b011) {
                         case 1: op = rv_op_cm_mvsa01; break;
                         case 3: op = rv_op_cm_mva01s; break;