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Thu, 18 May 2023 20:04:17 +0000 Received: from pps.filterd (NALASPPMTA04.qualcomm.com [127.0.0.1]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 34IK4Gh8013713; Thu, 18 May 2023 20:04:16 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA04.qualcomm.com (PPS) with ESMTPS id 3qmrx7jyxr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 May 2023 20:04:16 +0000 Received: from NALASPPMTA04.qualcomm.com (NALASPPMTA04.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34IK4FEJ013668; Thu, 18 May 2023 20:04:15 GMT Received: from hu-devc-sd-u20-a-1.qualcomm.com (hu-tsimpson-lv.qualcomm.com [10.47.204.221]) by NALASPPMTA04.qualcomm.com (PPS) with ESMTPS id 34IK4Fmu013633 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 May 2023 20:04:15 +0000 Received: by hu-devc-sd-u20-a-1.qualcomm.com (Postfix, from userid 47164) id 856176D6; Thu, 18 May 2023 13:04:13 -0700 (PDT) From: Taylor Simpson To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, peter.maydell@linaro.org, bcain@quicinc.com, quic_mathbern@quicinc.com, stefanha@redhat.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com Subject: [PULL v2 21/44] Hexagon (target/hexagon) Short-circuit packet predicate writes Date: Thu, 18 May 2023 13:03:48 -0700 Message-Id: <20230518200411.271148-22-tsimpson@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518200411.271148-1-tsimpson@quicinc.com> References: <20230518200411.271148-1-tsimpson@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: uBNHBI570DBjce_9LYOYgLRKK4ji8KVu X-Proofpoint-GUID: uBNHBI570DBjce_9LYOYgLRKK4ji8KVu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-18_15,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=815 malwarescore=0 impostorscore=0 bulkscore=0 mlxscore=0 clxscore=1015 adultscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305180165 Received-SPF: pass client-ip=205.220.180.131; envelope-from=tsimpson@qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In certain cases, we can avoid the overhead of writing to hex_new_pred_value and write directly to hex_pred. We consider predicate reads/writes when computing ctx->need_commit. The get_result_pred() function uses this field to decide between hex_new_pred_value and hex_pred. Then, we can early-exit from gen_pred_writes. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-13-tsimpson@quicinc.com> --- target/hexagon/genptr.h | 1 + target/hexagon/genptr.c | 15 ++++++++++++--- target/hexagon/translate.c | 14 +++++++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index 420867f934..e11ccc2358 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -35,6 +35,7 @@ void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot); void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot); TCGv gen_read_reg(TCGv result, int num); TCGv gen_read_preg(TCGv pred, uint8_t num); +TCGv get_result_pred(DisasContext *ctx, int pnum); void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val); void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val); void gen_set_usr_field(DisasContext *ctx, int field, TCGv val); diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 9858d7bc35..5025e172cf 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -110,8 +110,18 @@ static void gen_log_reg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 val) gen_log_reg_write(ctx, rnum + 1, val32); } +TCGv get_result_pred(DisasContext *ctx, int pnum) +{ + if (ctx->need_commit) { + return hex_new_pred_value[pnum]; + } else { + return hex_pred[pnum]; + } +} + void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) { + TCGv pred = get_result_pred(ctx, pnum); TCGv base_val = tcg_temp_new(); tcg_gen_andi_tl(base_val, val, 0xff); @@ -124,10 +134,9 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) * straight assignment. Otherwise, do an and. */ if (!test_bit(pnum, ctx->pregs_written)) { - tcg_gen_mov_tl(hex_new_pred_value[pnum], base_val); + tcg_gen_mov_tl(pred, base_val); } else { - tcg_gen_and_tl(hex_new_pred_value[pnum], - hex_new_pred_value[pnum], base_val); + tcg_gen_and_tl(pred, pred, base_val); } if (HEX_DEBUG) { tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 6fa885cf16..bcf64f725a 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -386,6 +386,14 @@ static bool need_commit(DisasContext *ctx) } } + /* Check for overlap between predicate reads and writes */ + for (int i = 0; i < ctx->preg_log_idx; i++) { + int pnum = ctx->preg_log[i]; + if (test_bit(pnum, ctx->pregs_read)) { + return true; + } + } + return false; } @@ -503,7 +511,7 @@ static void gen_start_packet(DisasContext *ctx) * Preload the predicated pred registers into hex_new_pred_value[pred_num] * Only endloop instructions conditionally write to pred registers */ - if (pkt->pkt_has_endloop) { + if (ctx->need_commit && pkt->pkt_has_endloop) { for (int i = 0; i < ctx->preg_log_idx; i++) { int pred_num = ctx->preg_log[i]; tcg_gen_mov_tl(hex_new_pred_value[pred_num], hex_pred[pred_num]); @@ -622,8 +630,8 @@ static void gen_reg_writes(DisasContext *ctx) static void gen_pred_writes(DisasContext *ctx) { - /* Early exit if the log is empty */ - if (!ctx->preg_log_idx) { + /* Early exit if not needed or the log is empty */ + if (!ctx->need_commit || !ctx->preg_log_idx) { return; }