From patchwork Tue Mar 21 10:25:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: qianfan X-Patchwork-Id: 1759378 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256 header.s=s110527 header.b=iiKCuHR0; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Pgnpn4RJfz1yWp for ; Tue, 21 Mar 2023 21:27:13 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1peZBT-0000SJ-Vf; Tue, 21 Mar 2023 06:25:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1peZBP-0000PM-N5; Tue, 21 Mar 2023 06:25:35 -0400 Received: from m12.mail.163.com ([220.181.12.215]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1peZBK-0008NI-IM; Tue, 21 Mar 2023 06:25:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=wXXoW yWKWWH2FjBzmJ6Ej1UtcbxrxEiAo5dH8WKonGY=; b=iiKCuHR02Fi5gvuxz7lTi y3hcQOW6dA21VqeTJ9k+GQgMGQT2aGYj4SSoEh4ynvmAUqDRy07HKSRsvDFs4oPO c02T4oAEYpXvMIfbEdq+D/a/atEMZkfpUd5swNJH0PQ8FO8wIxlFtlWd/Jnrx0ux X4ZWTHUOh6Fm2Kb91GN3ts= Received: from DESKTOP-B1R4FVG.localdomain (unknown [218.201.129.19]) by zwqz-smtp-mta-g5-1 (Coremail) with SMTP id _____wBnznIHhhlk7VIWAA--.11160S6; Tue, 21 Mar 2023 18:25:14 +0800 (CST) From: qianfanguijin@163.com To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Strahinja Jankovic , Peter Maydell , Beniamino Galvani , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Niek Linnenbank , qianfan Zhao Subject: [PATCH v1 04/11] hw: arm: allwinner-r40: Add 5 TWI controllers Date: Tue, 21 Mar 2023 18:25:03 +0800 Message-Id: <20230321102510.16754-5-qianfanguijin@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230321102510.16754-1-qianfanguijin@163.com> References: <20230321102510.16754-1-qianfanguijin@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wBnznIHhhlk7VIWAA--.11160S6 X-Coremail-Antispam: 1Uf129KBjvJXoW3Jr4kKw1xCw4DtFW3Kr15Arb_yoW7ZF48pF W7C390grW0gw18Ar4kKws3XrySy348Gr17K3WS9FWftr10gr4kXry2va1UCF45Krs7Way3 XrZ5JFWxG3W7taDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pR-J5rUUUUU= X-Originating-IP: [218.201.129.19] X-CM-SenderInfo: htld0w5dqj3xxmlqqiywtou0bp/1tbiXQc57VWBo+uC8QABsg Received-SPF: pass client-ip=220.181.12.215; envelope-from=qianfanguijin@163.com; helo=m12.mail.163.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: qianfan Zhao TWI(i2c) is designed to be used as an interface between CPU host and the serial 2-Wire bus. It can support all standard 2-Wire transfer, can be operated in standard mode(100kbit/s) or fast-mode, supporting data rate up to 400kbit/s. Signed-off-by: qianfan Zhao --- hw/arm/allwinner-r40.c | 47 ++++++++++++++++++++++++++++++---- include/hw/arm/allwinner-r40.h | 11 ++++++++ 2 files changed, 53 insertions(+), 5 deletions(-) diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index fde01783b1..9fa23e1f33 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -52,6 +52,11 @@ const hwaddr allwinner_r40_memmap[] = { [AW_R40_DEV_UART5] = 0x01c29400, [AW_R40_DEV_UART6] = 0x01c29800, [AW_R40_DEV_UART7] = 0x01c29c00, + [AW_R40_DEV_TWI0] = 0x01c2ac00, + [AW_R40_DEV_TWI1] = 0x01c2b000, + [AW_R40_DEV_TWI2] = 0x01c2b400, + [AW_R40_DEV_TWI3] = 0x01c2b800, + [AW_R40_DEV_TWI4] = 0x01c2c000, [AW_R40_DEV_GIC_DIST] = 0x01c81000, [AW_R40_DEV_GIC_CPU] = 0x01c82000, [AW_R40_DEV_GIC_HYP] = 0x01c84000, @@ -115,11 +120,6 @@ static struct AwR40Unimplemented r40_unimplemented[] = { { "uart7", 0x01c29c00, 1 * KiB }, { "ps20", 0x01c2a000, 1 * KiB }, { "ps21", 0x01c2a400, 1 * KiB }, - { "twi0", 0x01c2ac00, 1 * KiB }, - { "twi1", 0x01c2b000, 1 * KiB }, - { "twi2", 0x01c2b400, 1 * KiB }, - { "twi3", 0x01c2b800, 1 * KiB }, - { "twi4", 0x01c2c000, 1 * KiB }, { "scr", 0x01c2c400, 1 * KiB }, { "tvd-top", 0x01c30000, 4 * KiB }, { "tvd0", 0x01c31000, 4 * KiB }, @@ -167,6 +167,9 @@ enum { AW_R40_GIC_SPI_UART1 = 2, AW_R40_GIC_SPI_UART2 = 3, AW_R40_GIC_SPI_UART3 = 4, + AW_R40_GIC_SPI_TWI0 = 7, + AW_R40_GIC_SPI_TWI1 = 8, + AW_R40_GIC_SPI_TWI2 = 9, AW_R40_GIC_SPI_UART4 = 17, AW_R40_GIC_SPI_UART5 = 18, AW_R40_GIC_SPI_UART6 = 19, @@ -177,6 +180,8 @@ enum { AW_R40_GIC_SPI_MMC1 = 33, AW_R40_GIC_SPI_MMC2 = 34, AW_R40_GIC_SPI_MMC3 = 35, + AW_R40_GIC_SPI_TWI3 = 88, + AW_R40_GIC_SPI_TWI4 = 89, }; /* Allwinner R40 general constants */ @@ -262,6 +267,12 @@ static void allwinner_r40_init(Object *obj) object_initialize_child(obj, "mmc1", &s->mmc1, TYPE_AW_SDHOST_SUN5I); object_initialize_child(obj, "mmc2", &s->mmc2, TYPE_AW_SDHOST_SUN5I); object_initialize_child(obj, "mmc3", &s->mmc3, TYPE_AW_SDHOST_SUN5I); + + object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I); + object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I); + object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I); + object_initialize_child(obj, "twi3", &s->i2c3, TYPE_AW_I2C_SUN6I); + object_initialize_child(obj, "twi4", &s->i2c4, TYPE_AW_I2C_SUN6I); } static void allwinner_r40_realize(DeviceState *dev, Error **errp) @@ -429,6 +440,32 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_UART7), 115200, serial_hd(7), DEVICE_NATIVE_ENDIAN); + /* I2C */ + sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_R40_DEV_TWI0]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI0)); + + sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_R40_DEV_TWI1]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI1)); + + sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_R40_DEV_TWI2]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI2)); + + sysbus_realize(SYS_BUS_DEVICE(&s->i2c3), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c3), 0, s->memmap[AW_R40_DEV_TWI3]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c3), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI3)); + + sysbus_realize(SYS_BUS_DEVICE(&s->i2c4), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c4), 0, s->memmap[AW_R40_DEV_TWI4]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c4), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_TWI4)); + /* Unimplemented devices */ for (i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) { create_unimplemented_device(r40_unimplemented[i].device_name, diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h index dfb5eb609c..6a7e5c1e31 100644 --- a/include/hw/arm/allwinner-r40.h +++ b/include/hw/arm/allwinner-r40.h @@ -26,6 +26,7 @@ #include "hw/intc/arm_gic.h" #include "hw/sd/allwinner-sdhost.h" #include "hw/misc/allwinner-r40-ccu.h" +#include "hw/i2c/allwinner-i2c.h" #include "target/arm/cpu.h" #include "sysemu/block-backend.h" @@ -48,6 +49,11 @@ enum { AW_R40_DEV_UART5, AW_R40_DEV_UART6, AW_R40_DEV_UART7, + AW_R40_DEV_TWI0, + AW_R40_DEV_TWI1, + AW_R40_DEV_TWI2, + AW_R40_DEV_TWI3, + AW_R40_DEV_TWI4, AW_R40_DEV_GIC_DIST, AW_R40_DEV_GIC_CPU, AW_R40_DEV_GIC_HYP, @@ -89,6 +95,11 @@ struct AwR40State { AwSdHostState mmc2; AwSdHostState mmc3; AwR40ClockCtlState ccu; + AWI2CState i2c0; + AWI2CState i2c1; + AWI2CState i2c2; + AWI2CState i2c3; + AWI2CState i2c4; GICState gic; MemoryRegion sram_a1; MemoryRegion sram_a2;