diff mbox series

[5/5] target/tricore: Fix OPC2_32_BO_LD_BU_PREINC

Message ID 20230127120328.2520624-6-kbastian@mail.uni-paderborn.de
State New
Headers show
Series TriCore instruction bugfixes | expand

Commit Message

Bastian Koppelmann Jan. 27, 2023, 12:03 p.m. UTC 
we were sign extending the result of the load, while the instruction
clearly states that the result should be unsigned.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target/tricore/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Richard Henderson Jan. 27, 2023, 6:25 p.m. UTC | #1 
On 1/27/23 02:03, Bastian Koppelmann wrote:
> we were sign extending the result of the load, while the instruction
> clearly states that the result should be unsigned.
> 
> Signed-off-by: Bastian Koppelmann<kbastian@mail.uni-paderborn.de>
> ---
>   target/tricore/translate.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index b8e0969079..c17d19b83e 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -4964,7 +4964,7 @@  static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx)
         tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
         break;
     case OPC2_32_BO_LD_BU_PREINC:
-        gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
+        gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
         break;
     case OPC2_32_BO_LD_D_SHORTOFF:
         CHECK_REG_PAIR(r1);