| Message ID | 20221121103213.1675568-4-kraxel@redhat.com |
|---|---|
| State | New |
| Headers | show |
| Series | misc tweaks for kvm and the 64bit pci window | expand |
Dear Gerd, Thank you for the patch. Am 21.11.22 um 11:32 schrieb Gerd Hoffmann: > When the size of the physical address space is known (PhysBits is not > zero) move the 64bit pci io window to the end of the address space. It’d be great, if you elaborated, why this is an improvement. Kind regards, Paul > Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> > --- > src/fw/pciinit.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c > index badf13d3233b..ad6def93633b 100644 > --- a/src/fw/pciinit.c > +++ b/src/fw/pciinit.c > @@ -1128,6 +1128,14 @@ static void pci_bios_map_devices(struct pci_bus *busses) > r64_mem.base = le64_to_cpu(romfile_loadint("etc/reserved-memory-end", 0)); > if (r64_mem.base < 0x100000000LL + RamSizeOver4G) > r64_mem.base = 0x100000000LL + RamSizeOver4G; > + if (PhysBits) { > + u64 top = 1LL << PhysBits; > + u64 size = (ALIGN(sum_mem, (1LL<<30)) + > + ALIGN(sum_pref, (1LL<<30))); > + if (r64_mem.base < top - size) { > + r64_mem.base = top - size; > + } > + } > r64_mem.base = ALIGN(r64_mem.base, align_mem); > r64_mem.base = ALIGN(r64_mem.base, (1LL<<30)); // 1G hugepage > r64_pref.base = r64_mem.base + sum_mem;
On Mon, Nov 21, 2022 at 11:57:35AM +0100, Paul Menzel wrote: > Dear Gerd, > > > Thank you for the patch. > > Am 21.11.22 um 11:32 schrieb Gerd Hoffmann: > > When the size of the physical address space is known (PhysBits is not > > zero) move the 64bit pci io window to the end of the address space. > > It’d be great, if you elaborated, why this is an improvement. It makes seabios follow a common pattern. real mode address space has io resources mapped high (below 1M). 32-bit address space has io resources mapped high too (below 4G). This does the same for 64-bit resources. Physical hardware does simliar things, here is my workstation: # sudo cat /proc/iomem [ ... regions below 4G snipped ... ] 100000000-a36ffffff : System RAM 2e6000000-2e7002607 : Kernel code 2e7200000-2e7e84fff : Kernel rodata 2e8000000-2e8326e7f : Kernel data 2e8b6e000-2e8ffffff : Kernel bss a37000000-a37ffffff : RAM buffer 2000000000-2fffffffff : PCI Bus 0000:00 2ffff00000-2ffff0ffff : 0000:00:1f.3 2ffff10000-2ffff1ffff : 0000:00:14.0 2ffff10000-2ffff1ffff : xhci-hcd 2ffff20000-2ffff23fff : 0000:00:1f.3 2ffff20000-2ffff23fff : ICH HD audio 2ffff24000-2ffff240ff : 0000:00:1f.4 2ffff25000-2ffff25fff : 0000:00:16.0 2ffff25000-2ffff25fff : mei_me There is a larger gap between the end of memory and start of the pci io window. It's not the end of the *cpu* physical address space (that would be 7fffffffff aka phys-bits=39). Maybe there are additional constrains in the io chipset (which is a non-issue for virtual machines). take care, Gerd
diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index badf13d3233b..ad6def93633b 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -1128,6 +1128,14 @@ static void pci_bios_map_devices(struct pci_bus *busses) r64_mem.base = le64_to_cpu(romfile_loadint("etc/reserved-memory-end", 0)); if (r64_mem.base < 0x100000000LL + RamSizeOver4G) r64_mem.base = 0x100000000LL + RamSizeOver4G; + if (PhysBits) { + u64 top = 1LL << PhysBits; + u64 size = (ALIGN(sum_mem, (1LL<<30)) + + ALIGN(sum_pref, (1LL<<30))); + if (r64_mem.base < top - size) { + r64_mem.base = top - size; + } + } r64_mem.base = ALIGN(r64_mem.base, align_mem); r64_mem.base = ALIGN(r64_mem.base, (1LL<<30)); // 1G hugepage r64_pref.base = r64_mem.base + sum_mem;
When the size of the physical address space is known (PhysBits is not zero) move the 64bit pci io window to the end of the address space. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> --- src/fw/pciinit.c | 8 ++++++++ 1 file changed, 8 insertions(+)