| Message ID | 20221108040552.22175-11-tsimpson@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Hexagon (target/hexagon) performance and bug fixes | expand |
On 11/8/22 15:05, Taylor Simpson wrote: > static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) > { > + DisasContext *ctx = container_of(db, DisasContext, base); > + ctx->branch_cond = TCG_COND_NEVER; > } Typically this would go in hexagon_tr_init_disas_context as well, but I don't suppose it really matters. r~
> -----Original Message----- > From: Richard Henderson <richard.henderson@linaro.org> > Sent: Tuesday, November 8, 2022 1:24 AM > To: Taylor Simpson <tsimpson@quicinc.com>; qemu-devel@nongnu.org > Cc: philmd@linaro.org; ale@rev.ng; anjo@rev.ng; Brian Cain > <bcain@quicinc.com>; Matheus Bernardino (QUIC) > <quic_mathbern@quicinc.com> > Subject: Re: [PATCH v4 10/11] Hexagon (target/hexagon) Use direct block > chaining for direct jump/branch > > On 11/8/22 15:05, Taylor Simpson wrote: > > static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) > > { > > + DisasContext *ctx = container_of(db, DisasContext, base); > > + ctx->branch_cond = TCG_COND_NEVER; > > } > > Typically this would go in hexagon_tr_init_disas_context as well, but I don't > suppose it really matters. AFAICT, these are always called back to back. So, it's not clear to me what the distinction should be. Taylor
On 11/9/22 02:41, Taylor Simpson wrote: > > >> -----Original Message----- >> From: Richard Henderson <richard.henderson@linaro.org> >> Sent: Tuesday, November 8, 2022 1:24 AM >> To: Taylor Simpson <tsimpson@quicinc.com>; qemu-devel@nongnu.org >> Cc: philmd@linaro.org; ale@rev.ng; anjo@rev.ng; Brian Cain >> <bcain@quicinc.com>; Matheus Bernardino (QUIC) >> <quic_mathbern@quicinc.com> >> Subject: Re: [PATCH v4 10/11] Hexagon (target/hexagon) Use direct block >> chaining for direct jump/branch >> >> On 11/8/22 15:05, Taylor Simpson wrote: >>> static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) >>> { >>> + DisasContext *ctx = container_of(db, DisasContext, base); >>> + ctx->branch_cond = TCG_COND_NEVER; >>> } >> >> Typically this would go in hexagon_tr_init_disas_context as well, but I don't >> suppose it really matters. > > AFAICT, these are always called back to back. So, it's not clear to me what the distinction should be. ops->tb_start is called after gen_tb_start, so you can emit code that comes after the interrupt/icount check, but before the first guest instruction. Rarely needed, should probably be allowed to be NULL. r~
> -----Original Message----- > From: Richard Henderson <richard.henderson@linaro.org> > Sent: Tuesday, November 8, 2022 7:41 PM > To: Taylor Simpson <tsimpson@quicinc.com>; qemu-devel@nongnu.org > Cc: philmd@linaro.org; ale@rev.ng; anjo@rev.ng; Brian Cain > <bcain@quicinc.com>; Matheus Bernardino (QUIC) > <quic_mathbern@quicinc.com> > Subject: Re: [PATCH v4 10/11] Hexagon (target/hexagon) Use direct block > chaining for direct jump/branch > > >> -----Original Message----- > >> From: Richard Henderson <richard.henderson@linaro.org> > >> Sent: Tuesday, November 8, 2022 1:24 AM > >> To: Taylor Simpson <tsimpson@quicinc.com>; qemu-devel@nongnu.org > >> Cc: philmd@linaro.org; ale@rev.ng; anjo@rev.ng; Brian Cain > >> <bcain@quicinc.com>; Matheus Bernardino (QUIC) > >> <quic_mathbern@quicinc.com> > >> Subject: Re: [PATCH v4 10/11] Hexagon (target/hexagon) Use direct > >> block chaining for direct jump/branch > >> > >> On 11/8/22 15:05, Taylor Simpson wrote: > >>> static void hexagon_tr_tb_start(DisasContextBase *db, CPUState > *cpu) > >>> { > >>> + DisasContext *ctx = container_of(db, DisasContext, base); > >>> + ctx->branch_cond = TCG_COND_NEVER; > >>> } > >> > >> Typically this would go in hexagon_tr_init_disas_context as well, but > >> I don't suppose it really matters. > > > > AFAICT, these are always called back to back. So, it's not clear to me what > the distinction should be. > > ops->tb_start is called after gen_tb_start, so you can emit code that > ops->comes after the > interrupt/icount check, but before the first guest instruction. Rarely needed, > should probably be allowed to be NULL. OK, I will move this to init_disas_context. Thanks, Taylor
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 96509a4da7..aacf0b0921 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -57,6 +57,8 @@ typedef struct DisasContext { bool qreg_is_predicated[NUM_QREGS]; int qreg_log_idx; bool pre_commit; + TCGCond branch_cond; + target_ulong branch_dest; } DisasContext; static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index b8808ae17a..584e6415c0 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -484,7 +484,17 @@ static void gen_write_new_pc_pcrel(DisasContext *ctx, int pc_off, TCGCond cond, TCGv pred) { target_ulong dest = ctx->pkt->pc + pc_off; - gen_write_new_pc_addr(ctx, tcg_constant_tl(dest), cond, pred); + if (ctx->pkt->pkt_has_multi_cof) { + gen_write_new_pc_addr(ctx, tcg_constant_tl(dest), cond, pred); + } else { + /* Defer this jump to the end of the TB */ + ctx->branch_cond = TCG_COND_ALWAYS; + if (pred != NULL) { + ctx->branch_cond = cond; + tcg_gen_mov_tl(hex_branch_taken, pred); + } + ctx->branch_dest = dest; + } } static void gen_compare(TCGCond cond, TCGv res, TCGv arg1, TCGv arg2) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index fa6415936c..8e5814a3ea 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -116,10 +116,41 @@ static void gen_exec_counters(DisasContext *ctx) hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); } +static bool use_goto_tb(DisasContext *ctx, target_ulong dest) +{ + return translator_use_goto_tb(&ctx->base, dest); +} + +static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest) +{ + if (use_goto_tb(ctx, dest)) { + tcg_gen_goto_tb(idx); + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest); + tcg_gen_exit_tb(ctx->base.tb, idx); + } else { + tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest); + tcg_gen_lookup_and_goto_ptr(); + } +} + static void gen_end_tb(DisasContext *ctx) { gen_exec_counters(ctx); - tcg_gen_exit_tb(NULL, 0); + + if (ctx->branch_cond != TCG_COND_NEVER) { + if (ctx->branch_cond != TCG_COND_ALWAYS) { + TCGLabel *skip = gen_new_label(); + tcg_gen_brcondi_tl(ctx->branch_cond, hex_branch_taken, 0, skip); + gen_goto_tb(ctx, 0, ctx->branch_dest); + gen_set_label(skip); + gen_goto_tb(ctx, 1, ctx->next_PC); + } else { + gen_goto_tb(ctx, 0, ctx->branch_dest); + } + } else { + tcg_gen_lookup_and_goto_ptr(); + } + ctx->base.is_jmp = DISAS_NORETURN; } @@ -811,6 +842,8 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) { + DisasContext *ctx = container_of(db, DisasContext, base); + ctx->branch_cond = TCG_COND_NEVER; } static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
Direct block chaining is documented here https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining Recall that Hexagon allows packets with multiple jumps where only the first one with a true predicate will actually jump. We can use tcg_gen_goto_tb/tcg_gen_exit_tb when the packet contains a single PC-relative branch or jump. If not, we use tcg_gen_lookup_and_goto_ptr. We add the following to DisasContext in order to delay the branching until the end of packet commit (in gen_end_tb) branch_cond The TCGCond condition under which the branch is taken When branch_cond == TCG_COND_NEVER, there isn't a single direct branch in this packet. When branch_cond != TCG_COND_ALWAYS, the value is in hex_branch_taken branch_dest The destination of the branch Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> --- target/hexagon/translate.h | 2 ++ target/hexagon/genptr.c | 12 +++++++++++- target/hexagon/translate.c | 35 ++++++++++++++++++++++++++++++++++- 3 files changed, 47 insertions(+), 2 deletions(-)