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Fri, 28 Oct 2022 22:01:19 -0400 (EDT) From: Jiaxun Yang To: f4bug@amsat.org Cc: qemu-devel@nongnu.org, pavel.dovgalyuk@ispras.ru, Jiaxun Yang Subject: [PATCH 3/3] target/mips: Disable DSP ASE for Octeon68XX Date: Sat, 29 Oct 2022 03:00:30 +0100 Message-Id: <20221029020030.13936-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) In-Reply-To: <20221029020030.13936-1-jiaxun.yang@flygoat.com> References: <20221029020030.13936-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=64.147.123.24; envelope-from=jiaxun.yang@flygoat.com; helo=wout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org I don't have access to Octeon68XX hardware but accroading to my investigation Octeon never had DSP ASE support. As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 processor and I can confirm CP0C3_DSPP is read as 0 on that processor. Further more, in linux kernel: arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h cpu_has_dsp is overridden as 0. So I believe we shouldn't emulate DSP in QEMU as well. Signed-off-by: Jiaxun Yang Acked-by: Richard Henderson --- target/mips/cpu-defs.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 7f53c94ec8..480e60aeec 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -934,7 +934,7 @@ const mips_def_t mips_defs[] = (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) , + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) | (3U << CP0C4_MMUSizeExt), @@ -946,7 +946,7 @@ const mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x12F8FFFF, .SEGBITS = 42, .PABITS = 49, - .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP, + .insn_flags = CPU_MIPS64R2 | INSN_OCTEON, .mmu_type = MMU_TYPE_R4000, },