| Message ID | 20220628101737.786681-3-apatel@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | QEMU RISC-V nested virtualization fixes | expand |
On Tue, Jun 28, 2022 at 8:23 PM Anup Patel <apatel@ventanamicro.com> wrote: > > The minimum priv spec versino for mcountinhibit to v1.11 so that it > is not available for v1.10 (or lower). > > Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents") > Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/csr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index d65318dcc6..f7bfd2eab5 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -3944,7 +3944,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > write_mhpmcounter }, > > [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, > - write_mcountinhibit }, > + write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 }, > > [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, > write_mhpmevent }, > -- > 2.34.1 > >
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d65318dcc6..f7bfd2eab5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3944,7 +3944,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { write_mhpmcounter }, [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, - write_mcountinhibit }, + write_mcountinhibit, .min_priv_ver = PRIV_VERSION_1_11_0 }, [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent, write_mhpmevent },
The minimum priv spec versino for mcountinhibit to v1.11 so that it is not available for v1.10 (or lower). Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents") Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)