Message ID | 20220512031803.3315890-29-xiaoyao.li@intel.com |
---|---|
State | New |
Headers | show
Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=QZljr3DU; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=<UNKNOWN>) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KzHnT5VNGz9sG2 for <incoming@patchwork.ozlabs.org>; Thu, 12 May 2022 13:48:45 +1000 (AEST) Received: from localhost ([::1]:33374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>) id 1nozoh-0002KU-EJ for incoming@patchwork.ozlabs.org; Wed, 11 May 2022 23:48:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <xiaoyao.li@intel.com>) id 1nozNd-0005VH-0V for qemu-devel@nongnu.org; Wed, 11 May 2022 23:20:45 -0400 Received: from mga11.intel.com ([192.55.52.93]:31264) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <xiaoyao.li@intel.com>) id 1nozNb-0003Hf-Am for qemu-devel@nongnu.org; Wed, 11 May 2022 23:20:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652325643; x=1683861643; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Lh4ppGDQ1eZFnNDkiTMY5BSG4ZJaoqqHcvXD4R6VHIM=; b=QZljr3DUYGoS9rgnw7KnjS/ihOcI0ustQBKwkW2c9XkZcHRAoeIt3N4G cLt7U6olhPc5GVFz5akX1V6kPLSn4AJ45ZK3fvyS9SBd2dqERIyhSwP/U 3PzTuL9TViwH9PGFxB+3rCWqCjJTy3nTVgX7jptkbuXQVU/17OWFlbPX+ yu72yr3rTEVIBlzTVcB1Zdw/rKxGbDXyFENuxggLjND5iLpxETFwdSR0Z e2AZiqkt3cbg3yheR9uYfD1zy5bZSb01JE7ihUFEHv4lMg1EXne4swx4k pRv1QiPBXujRNaslYgYUNHtLSiLWtGDbCGB4bNr42SEW/azgvCEYznBw2 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10344"; a="267461345" X-IronPort-AV: E=Sophos;i="5.91,218,1647327600"; d="scan'208";a="267461345" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 20:20:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,218,1647327600"; d="scan'208";a="594456621" Received: from lxy-dell.sh.intel.com ([10.239.159.55]) by orsmga008.jf.intel.com with ESMTP; 11 May 2022 20:20:22 -0700 From: Xiaoyao Li <xiaoyao.li@intel.com> To: Paolo Bonzini <pbonzini@redhat.com>, Isaku Yamahata <isaku.yamahata@gmail.com>, isaku.yamahata@intel.com, Gerd Hoffmann <kraxel@redhat.com>, =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= <berrange@redhat.com>, =?utf-8?q?Phi?= =?utf-8?q?lippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>, Richard Henderson <richard.henderson@linaro.org>, "Michael S . Tsirkin" <mst@redhat.com>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, Cornelia Huck <cohuck@redhat.com>, Marcelo Tosatti <mtosatti@redhat.com>, Laszlo Ersek <lersek@redhat.com>, Eric Blake <eblake@redhat.com> Cc: Connor Kuehl <ckuehl@redhat.com>, erdemaktas@google.com, kvm@vger.kernel.org, qemu-devel@nongnu.org, seanjc@google.com, xiaoyao.li@intel.com Subject: [RFC PATCH v4 28/36] i386/tdx: Disable PIC for TDX VMs Date: Thu, 12 May 2022 11:17:55 +0800 Message-Id: <20220512031803.3315890-29-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220512031803.3315890-1-xiaoyao.li@intel.com> References: <20220512031803.3315890-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=192.55.52.93; envelope-from=xiaoyao.li@intel.com; helo=mga11.intel.com X-Spam_score_int: -51 X-Spam_score: -5.2 X-Spam_bar: ----- X-Spam_report: (-5.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.998, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> |
Series |
TDX QEMU support
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expand
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On Thu, May 12, 2022 at 11:17:55AM +0800, Xiaoyao Li wrote: > Legacy PIC (8259) cannot be supported for TDX VMs since TDX module > doesn't allow directly interrupt injection. Using posted interrupts > for the PIC is not a viable option as the guest BIOS/kernel will not > do EOI for PIC IRQs, i.e. will leave the vIRR bit set. > > Hence disable PIC for TDX VMs and error out if user wants PIC. Acked-by: Gerd Hoffmann <kraxel@redhat.com>
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 7ff4c6a9a7ca..59c7aa8f1818 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -333,6 +333,13 @@ int tdx_kvm_init(MachineState *ms, Error **errp) return -EINVAL; } + if (x86ms->pic == ON_OFF_AUTO_AUTO) { + x86ms->pic = ON_OFF_AUTO_OFF; + } else if (x86ms->pic == ON_OFF_AUTO_ON) { + error_setg(errp, "TDX VM doesn't support PIC"); + return -EINVAL; + } + if (!tdx_caps) { get_tdx_capabilities(); }
Legacy PIC (8259) cannot be supported for TDX VMs since TDX module doesn't allow directly interrupt injection. Using posted interrupts for the PIC is not a viable option as the guest BIOS/kernel will not do EOI for PIC IRQs, i.e. will leave the vIRR bit set. Hence disable PIC for TDX VMs and error out if user wants PIC. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> --- target/i386/kvm/tdx.c | 7 +++++++ 1 file changed, 7 insertions(+)