@@ -17,5 +17,5 @@ static inline bool regpairs_aligned(void *cpu_env)
return true;
}
-#endif /* ! TARGET_H */
+#endif /* TARGET_H */
@@ -17,5 +17,5 @@ static inline bool regpairs_aligned(void *cpu_env)
return false;
}
-#endif /* ! TARGET_H */
+#endif /* TARGET_H */
@@ -21,6 +21,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
+
#ifndef CHARDEV_INTERNAL_H
#define CHARDEV_INTERNAL_H
@@ -64,4 +65,4 @@ void mux_chr_send_all_event(Chardev *chr, QEMUChrEvent event);
Object *get_chardevs_root(void);
-#endif /* CHAR_MUX_H */
+#endif /* CHARDEV_INTERNAL_H */
@@ -21,6 +21,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
+
#ifndef BLOCK_INT_GLOBAL_STATE_H
#define BLOCK_INT_GLOBAL_STATE_H
@@ -326,4 +327,4 @@ static inline void assert_bdrv_graph_writable(BlockDriverState *bs)
assert(qemu_in_main_thread());
}
-#endif /* BLOCK_INT_GLOBAL_STATE */
+#endif /* BLOCK_INT_GLOBAL_STATE_H */
@@ -187,4 +187,4 @@ FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
#undef GEN_TRANSLATOR_LD
-#endif /* EXEC__TRANSLATOR_H */
+#endif /* EXEC__TRANSLATOR_H */
@@ -141,4 +141,4 @@ static inline bool get_default_nan_mode(float_status *status)
return status->default_nan_mode;
}
-#endif /* _SOFTFLOAT_HELPERS_H_ */
+#endif /* SOFTFLOAT_HELPERS_H */
@@ -93,4 +93,4 @@ struct AspeedGPIOState {
} sets[ASPEED_GPIO_MAX_NR_SETS];
};
-#endif /* _ASPEED_GPIO_H_ */
+#endif /* ASPEED_GPIO_H */
@@ -73,4 +73,4 @@ struct RXICUState {
#define TYPE_RX_ICU "rx-icu"
OBJECT_DECLARE_SIMPLE_TYPE(RXICUState, RX_ICU)
-#endif /* RX_ICU_H */
+#endif /* HW_INTC_RX_ICU_H */
@@ -47,4 +47,4 @@ struct AspeedHACEClass {
uint32_t hash_mask;
};
-#endif /* _ASPEED_HACE_H_ */
+#endif /* ASPEED_HACE_H */
@@ -44,4 +44,4 @@ typedef struct AspeedLPCState {
uint32_t hicr7;
} AspeedLPCState;
-#endif /* _ASPEED_LPC_H_ */
+#endif /* ASPEED_LPC_H */
@@ -29,4 +29,4 @@ struct AspeedSBCClass {
SysBusDeviceClass parent_class;
};
-#endif /* _ASPEED_SBC_H_ */
+#endif /* ASPEED_SBC_H */
@@ -101,4 +101,4 @@ struct AwSun8iEmacState {
};
-#endif /* HW_NET_ALLWINNER_SUN8I_H */
+#endif /* HW_NET_ALLWINNER_SUN8I_EMAC_H */
@@ -47,4 +47,4 @@ struct NvramClass {
void (*toggle_lock)(Nvram *obj, int lock);
};
-#endif /* HW_M48T59_H */
+#endif /* HW_RTC_M48T59_H */
@@ -56,4 +56,4 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
void rtc_set_memory(ISADevice *dev, int addr, int val);
int rtc_get_memory(ISADevice *dev, int addr);
-#endif /* MC146818RTC_H */
+#endif /* HW_RTC_MC146818RTC_H */
@@ -37,4 +37,4 @@ struct qemu_plugin_hwaddr {
bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
bool is_store, struct qemu_plugin_hwaddr *data);
-#endif /* _PLUGIN_MEMORY_H_ */
+#endif /* PLUGIN_MEMORY_H */
@@ -41,4 +41,4 @@ GSList *read_self_maps(void);
*/
void free_self_maps(GSList *info);
-#endif /* _SELFMAP_H_ */
+#endif /* SELFMAP_H */
@@ -39,4 +39,4 @@ static inline void record_syscall_return(void *cpu, int num, abi_long ret)
}
-#endif /* _SYSCALL_TRACE_H_ */
+#endif /* SYSCALL_TRACE_H */
@@ -22,4 +22,4 @@
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
-#endif /* TARGET_SIGNAL_H */
+#endif /* HEXAGON_TARGET_SIGNAL_H */
@@ -247,4 +247,4 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
#include "exec/cpu-all.h"
-#endif /* !defined (QEMU_AVR_CPU_H) */
+#endif /* QEMU_AVR_CPU_H */
@@ -32,4 +32,4 @@ extern DECLARE_BITMAP(opcode_attribs[XX_LAST_OPCODE], A_ZZ_LASTATTRIB);
#define GET_ATTRIB(opcode, attrib) \
test_bit(attrib, opcode_attribs[opcode])
-#endif /* ATTRIBS_H */
+#endif /* HEXAGON_ATTRIBS_H */
@@ -43,11 +43,9 @@
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
#ifndef XTENSA_CONFIG_CORE_MATMAP_H
#define XTENSA_CONFIG_CORE_MATMAP_H
-
/*----------------------------------------------------------------------
CACHE (MEMORY ACCESS) ATTRIBUTES
----------------------------------------------------------------------*/
@@ -713,5 +711,5 @@
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
+#endif /* XTENSA_CONFIG_CORE_MATMAP_H */
@@ -43,11 +43,9 @@
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
#ifndef XTENSA_CONFIG_CORE_MATMAP_H
#define XTENSA_CONFIG_CORE_MATMAP_H
-
/*----------------------------------------------------------------------
CACHE (MEMORY ACCESS) ATTRIBUTES
----------------------------------------------------------------------*/
@@ -308,5 +306,5 @@
-#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
+#endif /* XTENSA_CONFIG_CORE_MATMAP_H */