From patchwork Wed Mar 30 12:56:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 1611153 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=greensocs.com header.i=@greensocs.com header.a=rsa-sha256 header.s=mail header.b=fxJqFatK; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KT78v00Krz9sFk for ; Thu, 31 Mar 2022 00:49:49 +1100 (AEDT) Received: from localhost ([::1]:58204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nZYhl-0002Gv-Dg for incoming@patchwork.ozlabs.org; Wed, 30 Mar 2022 09:49:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:52108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZXtE-0008GG-4A; Wed, 30 Mar 2022 08:57:32 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:41276) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZXtC-0004bf-BD; Wed, 30 Mar 2022 08:57:31 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPS id 3F4B321EDD; Wed, 30 Mar 2022 12:56:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1648645017; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AEeV3pdJjggFAgny3pSiPS5I29jbbs1q3Rp1FOMlriU=; b=fxJqFatKOJHc36kZtOyuEeFeIyYA3RKJqT30O49+s/4Y/q90h48PLenwDNPQ7ohljjHR51 w7v70xdZ+A3+RpFy+J+K0vG3/BoTfFHfTUXh1FUS2NN4MsaejBsNVNUbw8Z1RipjqC7AIH KpdHBDYcVp0hSC9v1JsahcuR65OutIo= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [RFC PATCH 17/18] hw/riscv/riscv_hart: remove temporary features Date: Wed, 30 Mar 2022 14:56:38 +0200 Message-Id: <20220330125639.201937-18-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330125639.201937-1-damien.hedde@greensocs.com> References: <20220330125639.201937-1-damien.hedde@greensocs.com> MIME-Version: 1.0 X-Spam: Yes Received-SPF: pass client-ip=5.135.226.135; envelope-from=damien.hedde@greensocs.com; helo=beetle.greensocs.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Peter Maydell , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, Alistair Francis , mark.burton@greensocs.com, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , qemu-arm@nongnu.org, Palmer Dabbelt , Vijai Kumar K , "Edgar E. Iglesias" , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that we updated all riscv machines, we can remove the temporary realize helper and the alias property. Signed-off-by: Damien Hedde --- include/hw/riscv/riscv_hart.h | 3 --- hw/riscv/riscv_hart.c | 14 -------------- 2 files changed, 17 deletions(-) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 65ac0d2bc4..acf5ee8575 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -56,7 +56,4 @@ static inline unsigned riscv_array_get_num_harts(RISCVHartArrayState *s) return CPUS(s)->topology.cpus; } -/* Temporary function until we migrated the riscv hart array to simple device */ -void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp); - #endif diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 1b4ff7e3c6..ea798de5d5 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -27,13 +27,6 @@ #include "hw/riscv/riscv_hart.h" #include "hw/cpu/cpus.h" -void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp) -{ - /* disable the clustering */ - cpus_disable_clustering(CPUS(state)); - qdev_realize(DEVICE(state), NULL, errp); -} - static Property riscv_harts_props[] = { DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, @@ -52,12 +45,6 @@ static void riscv_harts_configure_cpu(CpusState *base, CPUState *cpu, cpuenv->mhartid = s->hartid_base + i; } -static void riscv_harts_init(Object *obj) -{ - /* add a temporary property to keep num-harts */ - object_property_add_alias(obj, "num-harts", obj, "num-cpus"); -} - static void riscv_harts_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -73,7 +60,6 @@ static const TypeInfo riscv_harts_info = { .name = TYPE_RISCV_HART_ARRAY, .parent = TYPE_CPUS, .instance_size = sizeof(RISCVHartArrayState), - .instance_init = riscv_harts_init, .class_init = riscv_harts_class_init, };