diff mbox series

[v4,42/47] target/ppc: Refactor VSX_MAX_MINC helper

Message ID 20220222143646.1268606-43-matheus.ferst@eldorado.org.br
State New
Headers show
Series target/ppc: PowerISA Vector/VSX instruction batch | expand

Commit Message

Matheus K. Ferst Feb. 22, 2022, 2:36 p.m. UTC 
From: Víctor Colombo <victor.colombo@eldorado.org.br>

Refactor xs{max,min}cdp VSX_MAX_MINC helper to prepare for
xs{max,min}cqp implementation.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/fpu_helper.c | 23 +++++++++--------------
 1 file changed, 9 insertions(+), 14 deletions(-)

Comments

Richard Henderson Feb. 23, 2022, 12:40 a.m. UTC | #1 
On 2/22/22 04:36, matheus.ferst@eldorado.org.br wrote:
> -#define VSX_MAX_MINC(name, max)                                               \
> +#define VSX_MAX_MINC(name, op, tp, fld)                                       \
>   void helper_##name(CPUPPCState *env,                                          \
>                      ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)               \
>   {                                                                             \
>       ppc_vsr_t t = { };                                                        \
>       bool vxsnan_flag = false, vex_flag = false;                               \
>                                                                                 \
> -    if (unlikely(float64_is_any_nan(xa->VsrD(0)) ||                           \
> -                 float64_is_any_nan(xb->VsrD(0)))) {                          \
> -        if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||         \
> -            float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {         \
> +    if (unlikely(tp##_is_any_nan(xa->fld) ||                                  \
> +                 tp##_is_any_nan(xb->fld))) {                                 \
> +        if (tp##_is_signaling_nan(xa->fld, &env->fp_status) ||                \
> +            tp##_is_signaling_nan(xb->fld, &env->fp_status)) {                \
>               vxsnan_flag = true;                                               \
>           }                                                                     \
> -        t.VsrD(0) = xb->VsrD(0);                                              \
> -    } else if ((max &&                                                        \
> -               !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) ||     \
> -               (!max &&                                                       \
> -               float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) {      \
> -        t.VsrD(0) = xa->VsrD(0);                                              \
> +        t.fld = xb->fld;                                                      \
>       } else {                                                                  \
> -        t.VsrD(0) = xb->VsrD(0);                                              \
> +        t.fld = tp##_##op(xa->fld, xb->fld, &env->fp_status);                 \
>       }                                                                         \
>                                                                                 \
>       vex_flag = fpscr_ve & vxsnan_flag;                                        \

I think this would be simpler to utilize the result of the compare vs nans:

     bool first;

     if (max) {
         first = tp##_le_quiet(xb->fld, xa->fld, status);
     } else {
         first = tp##_lt_quiet(xa->fld, xb->fld, status);
     }
     if (first) {
         t.fld = xa->fld;
     } else {
         t.fld = xb->fld;
         if (flags & float_flag_invalid_snan) {
             float_invalid_op_vxsnan(env, retaddr);
         }
     }
     xt = *t;


r~
diff mbox series

Patch

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 7ae576cba9..f6eb8bf2d8 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2536,27 +2536,22 @@  VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
 VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
 
-#define VSX_MAX_MINC(name, max)                                               \
+#define VSX_MAX_MINC(name, op, tp, fld)                                       \
 void helper_##name(CPUPPCState *env,                                          \
                    ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)               \
 {                                                                             \
     ppc_vsr_t t = { };                                                        \
     bool vxsnan_flag = false, vex_flag = false;                               \
                                                                               \
-    if (unlikely(float64_is_any_nan(xa->VsrD(0)) ||                           \
-                 float64_is_any_nan(xb->VsrD(0)))) {                          \
-        if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||         \
-            float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {         \
+    if (unlikely(tp##_is_any_nan(xa->fld) ||                                  \
+                 tp##_is_any_nan(xb->fld))) {                                 \
+        if (tp##_is_signaling_nan(xa->fld, &env->fp_status) ||                \
+            tp##_is_signaling_nan(xb->fld, &env->fp_status)) {                \
             vxsnan_flag = true;                                               \
         }                                                                     \
-        t.VsrD(0) = xb->VsrD(0);                                              \
-    } else if ((max &&                                                        \
-               !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) ||     \
-               (!max &&                                                       \
-               float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) {      \
-        t.VsrD(0) = xa->VsrD(0);                                              \
+        t.fld = xb->fld;                                                      \
     } else {                                                                  \
-        t.VsrD(0) = xb->VsrD(0);                                              \
+        t.fld = tp##_##op(xa->fld, xb->fld, &env->fp_status);                 \
     }                                                                         \
                                                                               \
     vex_flag = fpscr_ve & vxsnan_flag;                                        \
@@ -2568,8 +2563,8 @@  void helper_##name(CPUPPCState *env,                                          \
     }                                                                         \
 }                                                                             \
 
-VSX_MAX_MINC(XSMAXCDP, 1);
-VSX_MAX_MINC(XSMINCDP, 0);
+VSX_MAX_MINC(XSMAXCDP, maxnum, float64, VsrD(0));
+VSX_MAX_MINC(XSMINCDP, minnum, float64, VsrD(0));
 
 #define VSX_MAX_MINJ(name, max)                                               \
 void helper_##name(CPUPPCState *env,                                          \