| Message ID | 20220119113754.20323-15-liweiwei@iscas.ac.cn |
|---|---|
| State | New |
| Headers | show |
| Series | support subsets of scalar crypto extension | expand |
On Wed, Jan 19, 2022 at 11:09 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b487a8282c..04e8e8d3c6 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -694,7 +694,20 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), > + DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), > + DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), > + DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > + DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), > + DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), > + DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), > + DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), > + DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), > + DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), > + DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), > + DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), > + DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), > + DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), > > /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > -- > 2.17.1 > >
在 2022/1/21 上午8:35, Alistair Francis 写道: > On Wed, Jan 19, 2022 at 11:09 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > Alistair > Thanks for your comments. Regards, Weiwei Li >> --- >> target/riscv/cpu.c | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index b487a8282c..04e8e8d3c6 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -694,7 +694,20 @@ static Property riscv_cpu_properties[] = { >> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), >> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), >> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), >> + DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), >> + DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), >> + DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), >> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), >> + DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), >> + DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), >> + DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), >> + DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), >> + DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), >> + DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), >> + DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), >> + DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), >> + DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), >> + DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), >> >> /* These are experimental so mark with 'x-' */ >> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), >> -- >> 2.17.1 >> >>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b487a8282c..04e8e8d3c6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -694,7 +694,20 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), + DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), + DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), + DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), + DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), + DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), + DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), + DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), + DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), + DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), + DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), + DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), + DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),