diff mbox series

[v6,01/22] target/riscv: Adjust pmpcfg access with mxl

Message ID 20220113114004.286796-2-zhiwei_liu@c-sky.com
State New
Headers show
Series Support UXL filed in xstatus | expand

Commit Message

LIU Zhiwei Jan. 13, 2022, 11:39 a.m. UTC 
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/csr.c | 19 +++++++++++++++++++
 target/riscv/pmp.c | 12 ++++--------
 2 files changed, 23 insertions(+), 8 deletions(-)

Comments

Alistair Francis Jan. 19, 2022, 3:20 a.m. UTC | #1 
On Thu, Jan 13, 2022 at 9:41 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 19 +++++++++++++++++++
>  target/riscv/pmp.c | 12 ++++--------
>  2 files changed, 23 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index adb3d4381d..e7578f3e0f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1493,9 +1493,23 @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
>      return RISCV_EXCP_NONE;
>  }
>
> +static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
> +{
> +    /* TODO: RV128 restriction check */
> +    if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
> +        return false;
> +    }
> +    return true;
> +}
> +
>  static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
>                                    target_ulong *val)
>  {
> +    uint32_t reg_index = csrno - CSR_PMPCFG0;
> +
> +    if (!check_pmp_reg_index(env, reg_index)) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
>      *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
>      return RISCV_EXCP_NONE;
>  }
> @@ -1503,6 +1517,11 @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
>  static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
>                                     target_ulong val)
>  {
> +    uint32_t reg_index = csrno - CSR_PMPCFG0;
> +
> +    if (!check_pmp_reg_index(env, reg_index)) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
>      pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
>      return RISCV_EXCP_NONE;
>  }
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 54abf42583..81b61bb65c 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -463,16 +463,11 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
>  {
>      int i;
>      uint8_t cfg_val;
> +    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
>
>      trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
>
> -    if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
> -        qemu_log_mask(LOG_GUEST_ERROR,
> -                      "ignoring pmpcfg write - incorrect address\n");
> -        return;
> -    }
> -
> -    for (i = 0; i < sizeof(target_ulong); i++) {
> +    for (i = 0; i < pmpcfg_nums; i++) {
>          cfg_val = (val >> 8 * i)  & 0xff;
>          pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
>      }
> @@ -490,8 +485,9 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
>      int i;
>      target_ulong cfg_val = 0;
>      target_ulong val = 0;
> +    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
>
> -    for (i = 0; i < sizeof(target_ulong); i++) {
> +    for (i = 0; i < pmpcfg_nums; i++) {
>          val = pmp_read_cfg(env, (reg_index * 4) + i);
>          cfg_val |= (val << (i * 8));
>      }
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index adb3d4381d..e7578f3e0f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1493,9 +1493,23 @@  static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
+{
+    /* TODO: RV128 restriction check */
+    if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
+        return false;
+    }
+    return true;
+}
+
 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
+    uint32_t reg_index = csrno - CSR_PMPCFG0;
+
+    if (!check_pmp_reg_index(env, reg_index)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
     return RISCV_EXCP_NONE;
 }
@@ -1503,6 +1517,11 @@  static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
                                    target_ulong val)
 {
+    uint32_t reg_index = csrno - CSR_PMPCFG0;
+
+    if (!check_pmp_reg_index(env, reg_index)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
     return RISCV_EXCP_NONE;
 }
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 54abf42583..81b61bb65c 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -463,16 +463,11 @@  void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
 {
     int i;
     uint8_t cfg_val;
+    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
 
     trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
 
-    if ((reg_index & 1) && (sizeof(target_ulong) == 8)) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "ignoring pmpcfg write - incorrect address\n");
-        return;
-    }
-
-    for (i = 0; i < sizeof(target_ulong); i++) {
+    for (i = 0; i < pmpcfg_nums; i++) {
         cfg_val = (val >> 8 * i)  & 0xff;
         pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
     }
@@ -490,8 +485,9 @@  target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
     int i;
     target_ulong cfg_val = 0;
     target_ulong val = 0;
+    int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
 
-    for (i = 0; i < sizeof(target_ulong); i++) {
+    for (i = 0; i < pmpcfg_nums; i++) {
         val = pmp_read_cfg(env, (reg_index * 4) + i);
         cfg_val |= (val << (i * 8));
     }