| Message ID | 20211217233456.1475527-1-f4bug@amsat.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: Align vector registers to 16 bytes | expand |
On 12/17/21 3:34 PM, Philippe Mathieu-Daudé wrote: > Align fpr_t to 16 bytes to be able to use the TCG "Generic" > vector operation expansion API from "tcg/tcg-op-gvec.h", > otherwise we trigger assertions in check_size_align(). > > See commits ec8e23e37f8 (s390x) and 11e2bfef799 (i386) > for similar justifications. > > Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org> > --- > target/mips/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 56b1cbd091d..15b983f7104 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -30,7 +30,7 @@ union fpr_t { uint32_t w[2]; /* binary single fixed-point */ /* FPU/MSA register mapping is not tested on big-endian hosts. */ wr_t wr; /* vector data */ -}; +} QEMU_ALIGNED(16); /* *define FP_ENDIAN_IDX to access the same location * in the fpr_t union regardless of the host endianness
Align fpr_t to 16 bytes to be able to use the TCG "Generic" vector operation expansion API from "tcg/tcg-op-gvec.h", otherwise we trigger assertions in check_size_align(). See commits ec8e23e37f8 (s390x) and 11e2bfef799 (i386) for similar justifications. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)